L2 Ce Space Allocation Register Fields - Texas Instruments TMS320C6201 Reference Manual

Tms320c6000 series peripherals

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L2 Description

Figure 4–15. L2 CE Space Allocation Register Fields

The memory attribute registers (MARs) can be programmed to turn on caching

of each of the external chip enable (CE) spaces. In this way, you can perform

single word reads to external mapped devices. Without this feature any

external read would always read an entire L2 line of data. Each of the four CE

spaces is divided into four ranges, each of which maps the least significant bit

of an MAR register. If an MAR register is set, the corresponding address range

is cached by the L2. At reset, the MAR registers are set to 0. To begin caching

data in the L2, you must initialize the appropriate MAR register to 1. The MAR

registers define cacheability for the EMIF only. Addresses accessed by the

EMIF which are not defined by the MAR registers are always cacheable.

Figure 4–15 shows the format for the MARs. Table 4–3 illustrates which ad-

dress range each MAR bit enables for caching.

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