Tms320C6211/C6711 Block Diagram; Tms320C6211/C6711 Internal Memory Configurations; Tms320C6211/C6711 Cache Architectures - Texas Instruments TMS320C6201 Reference Manual

Overview
4.1 Overview
Figure 4–1. TMS320C6211/C6711 Block Diagram
External
memory
interface
(EMIF)
Multichannel
buffered
serial port 1
(McBSP 1)
Multichannel
buffered
serial port 0
(McBSP 0)
Host port
interface
(HPI)
Power down logic
Table 4–1. TMS320C6211/C6711 Internal Memory Configurations
Internal
Memory
Device CPU Architecture
'C6211/ 6200 Harvard (L1)
C6711 Unified (L2)
Table 4–2. TMS320C6211/C6711 Cache Architectures
4-2
Figure 4–1 illustrates how the L1P, L1D, and L2 are arranged in the
TMS320C6211/C6711. Figure 4–2 illustrates the bus connections between
the CPU, internal memories, and the enhanced DMA for the 'C6211, and.
Enhanced L2 memory
DMA 4 banks
controller 64K bytes
Timer 1
Total Memory
(Bytes)
72K
Cache Space Size (Bytes)
L1P 4K
L1D 4K
L2 64K
L1P cache
direct mapped
4K bytes
C6200B CPU
Instruction fetch
Instruction dispatch
Instruction decode
Data path 1
A register file
L1 S1 M1 D1
L1D cache
2-way set
Timer 0
associative
4K bytes
Program Memory Data Memory
(Bytes) (Bytes)
4K (cache) 4K (cache)
Associativity
Direct mapped
2-way
1- to 4-way
Control
registers
In-circuit
emulation
Data path 2
B register file
D2 M2 S2 L2
Unified Memory
(Bytes)
64K (map/cache)
Line Size (Bytes)
64
32
128