Expansion Bus External Address Register; Expansion Bus Host Port Interface Control (Xbhc) Register - Texas Instruments TMS320C6201 Reference Manual

Expansion Bus Host Port Operation
8.5.1.3 Expansion Bus Internal Master Address Register
Figure 8–16. Expansion Bus Internal Master Address Register
31

8.5.1.4 Expansion Bus External Address Register

Figure 8–17. Expansion Bus External Address Register
31
8.5.1.5 Expansion Bus Host Port Interface Control Register
8-24
This register is used when the host port operates either in synchronous or
asynchronous mode. The 'C6202 does not have access to the XBISA register
content. Burst transfers in the synchronous host-port mode are always
expected to occur with autoincrement (AINC bit should be set to zero).
The expansion bus internal master address (XBIMA) register, shown in
Figure 8–16, specifies the source or destination address in the DSP memory
map where the transaction starts. This register is set by the 'C6202 when the
DSP wants to initiate transfer on the expansion bus. Since all tranfers have a
width of one word, the XBIMA register is incremented by four after each trans-
fer.
This register is used when the host port operates in synchronous mode.
RW,+0000 0000 0000 0000 0000 0000 0000 0000
This register is set by the 'C6202 when the DSP wants to initiate transfer on
the expansion bus. The content of the XBEA register, shown in Figure 8–17,
appears on the XD[31:0] lines during an address phase of the transfer initiated
by the DSP. The expansion bus external address (XBEA) specifies where in
the external slave memory map the data is accessed. Since all tranfers have
a width of one word, the XBEA register is incremented by four after each trans-
fer.
This register is used when the host port operates in synchronous mode.
RW,+0000 0000 0000 0000 0000 0000 0000 0000
The expansion bus host port interface control (XBHC) register (shown in
Figure 8–18 and described in Table 8–15) configures expansion bus host port
parameters.
XBIMA
XBEA
0
0