L1P Flush Base Address Register Fields (L1Pfbar); L1P Flush Word Count Register Fields (L1Pfwc) - Texas Instruments TMS320C6201 Reference Manual

L1P Description
Figure 4–6. L1P Flush Base Address Register Fields (L1PFBAR
31
Figure 4–7. L1P Flush Word Count Register Fields (L1PFWC
31
4-8
The second method for invalidating the L1P requires the L1PFBAR and
L1PFWC registers. This is useful for invalidating a block of data in the L1P.
You must first write a word–aligned address into the L1PFBAR. This value is
the starting address for the invalidation. The number of words to be invali-
dated will be equal to the value written into the L1PFWC register. The L1P
searches for and invalidates all lines whose external memory address falls
within the range from L1PFBAR to L1PFBAR+L1PFWC–4. If L1PFBAR or
L1PFWC are not aligned to the L1P line size (16 words), all lines which contain
any address in the specified range are invalidated. Using this block invalida-
tion will not stall any pending CPU accesses. The block invalidation begins
when the L1PFWC is written, therefore you should take care to ensure that the
L1PFBAR register is set up correctly prior to writing the L1PFWC. Figure 4–6
and Figure 4–7 show the format for the L1PFBAR and L1PFWC.
L1P flush base address
16
rsvd
R,+x
RW,+x
15
L1P flush word count
)
)
RW,+x
0
0