Conflicting Internal Memory Accesses To The Same Block; (Tms320C6201 Revisions 2 And 3) - Texas Instruments TMS320C6201 Reference Manual

Internal Data Memory Organization
Figure 2–7. Conflicting Internal Memory Accesses to the Same Block

(TMS320C6201 Revisions 2 and 3)

DA1
DA2 2:0 000
Byte 000
001
010
011
100
101
110
111
Halfword 000
010
100
110
Word 000
100
Note: Conflicts shown in shaded areas.
2-16
Loads and stores from the same execute packet are seen by the data memory
controller during the same CPU cycle. Loads and stores from future or pre-
vious CPU cycles do not cause wait states for the internal data memory ac-
cesses in the current cycle. Thus, internal data memory access causes a wait
state only when a conflict occurs between instructions in the same fetch packet
accessing the same 16-bit wide bank. This conflict is an internal memory con-
flict. The data memory controller stalls the CPU for one CPU clock, serializes
the accesses, and performs each access separately. In prioritizing the two ac-
cesses, any load occurs before any store access. A load in parallel with a store
always has priority over the store. If both the load and the store access the
same resource (for example, the EMIF, or peripheral bus, internal memory
block), the load always occurs before the store. If both accesses are stores,
the access from DA1 takes precedence over the access from DA2. If both ac-
cesses are loads, the access from DA2 takes precedence over the access
from DA1. Figure 3–3 shows what access conditions cause internal memory
conflicts when the CPU makes two data accesses (on DA1 and DA2).
Byte
001 010 011 100 101 110 111 000
Halfword Word
010 100 110 000 100