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Figure 7–5. Select Input Logic
Figure 7–5 shows the equivalent circuit of the HCS, HDS1, and HDS2 inputs.
HDS1
HDS2
HCS
Used together, HCS, HDS1, and HDS2 generate an active (low) internal
HSTROBE signal. HSTROBE is active (low) only when both HCS is active and
either (but not both) HDS1 or HDS2 is active. The falling edge of HSTROBE
when HAS is tied inactive (high) samples HCNTL[1:0], HHWIL, and HR/W.
Therefore, the latest of HDS1 , HDS2, or HCS controls the sampling time. HCS
serves as the enable input for the HPI and must be low during an access. How-
ever, because the HSTROBE signal determines the actual boundaries be-
tween accesses, HCS can stay low between successive accesses as long as
both HDS1 and HDS2 transition appropriately.
Hosts with separate read and write strobes connect these strobes to either
HDS1 or HDS2. Hosts with a single data strobe connect it to either HDS1 or
a HDS2, tying the unused pin high. Regardless of HDS1 and HDS2 connec-
tions, HR/W is required to determine the direction of transfer. Because HDS1
and HDS2 are internally exclusive-NORed, hosts with a high true data strobe
can connect this strobe to either HDS1 or HDS2 with the other signal tied low.
HSTROBE is used for four purposes:
On a read, the falling edge of HSTROBE initiates HPI read accesses for
all access types.
On a write, the rising edge of HSTROBE initiates HPI write accesses for
all access types.
The falling edge latches the HPI control inputs, including HHWIL, HR/W,
and HCNTL[1:0]. HAS also affects latching of control inputs. See section
7.2.8 for a description of HAS.
The rising edge of HSTROBE latches the HBE[1:0] input as well as the
data to be written.
HCS gates the HRDY output. In other words, a not-ready condition is indicated
by the HRDY pin being driven high only if HCS is active (low). Otherwise HRDY
is active (low).
HPI Signal Descriptions
HSTROBE (internal signal)
Host-Port Interface
7-11
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