Tms320C6211/C6711 Block Diagram - Texas Instruments TMS320C6201 Reference Manual

Overview
6.1 Overview
Figure 6–1. TMS320C6211/C6711 Block Diagram
External
memory
interface
(EMIF)
Multi-channel
buffered
serial port 1
(McBSP 1)
Multi-channel
buffered
serial port 0
(McBSP 0)
Host port
interface
(HPI)
Power down logic
TMS320C6211/C6711 Digital Signal Processor
6-2
The TMS320C6211/C6711 device performs data transfers between on-chip
and/or off-chip locations using either the CPU or the enhanced direct memory
access (EDMA) controller. Typically, block data transfers and transfer re-
quests from peripherals are performed by the EDMA thus relieving the CPU
to do performance-intensive operations.
The EDMA controller in the 'C6211/C6711 is different in architecture to the
previous TMS320C6000 devices. The EDMA includes several enhancements
to the 'C6201/'C6701 DMA in that it provides 16 channels with programmable
priority, and the ability to link data transfers. The EDMA allows movement of
data to/from internal memory (L2 SRAM), peripherals, and between external
memory spaces.
Enhanced
DMA
controller
Timer 1
L1P
controller
Instruction fetch
Instruction dispatch
Instruction decode
Data path 1
A register file
L1 S1 M1 D1
controller
Timer 0
L1P cache direct mapped
4K bytes
CPU core
Control registers
In-circuit emulation
Data path 2
B register file
D2 M2 S2
L1D cache
L1D
2-way set
associative
4K bytes
L2