9.5 Sbsram Interface; Sbsram In Linear Burst Mode - Texas Instruments TMS320C6201 Reference Manual

9.5 SBSRAM Interface

Table 9–16. SBSRAM in Linear Burst Mode
As shown in Figure 9–30 ('C6201/C6202/C6701) and Figure 9–31
('C6211/C6711), the EMIF interfaces directly to industry-standard synchro-
nous burst SRAMs (SBSRAMS). This memory interface allows a high-speed
memory interface without some of the limitations of SDRAM. Most notably,
since SBSRAMs are SRAM devices, random accesses in the same direction
can occur in a single cycle. The SBSRAM interface can run at either the CPU
clock speed or at 1/2 of this rate for the 'C6201 and 'C6701. The selection is
made based on the setting of the SSCRT bit in the EMIF global control register.
For the 'C6202 the interface operates at the 1/2 rate only, and for the
'C6211/C6711, the SBSRAM runs off an externally provided clock.
The four SBSRAM control pins are latched by the SBSRAM on the rising SSCLK
edge to determine the current operation. These pins are listed in Table 9–17.
These signals are valid only if the chip select line for the SBSRAM is low.
For the 'C6201/6202/6701, the ADV signal of the SBSRAM is pulled high. This
disables the internal burst advance counter of the SBSRAM. This interface al-
lows bursting by strobing a new address into the SBSRAM on every cycle.
The 'C6211/C6711 interface takes advantage of the internal advance counter
of the SBSRAM. For this interface, the ADV signal is pulled low, so that every
access to the SBSRAM from the 'C6211/C6711 is assumed to be a four word
burst. If random addressing is required for a given access, the 'C6211/C6711
can perform this by overriding the burst feature of the SBSRAM and strobing
a new command into the SBSRAM on every cycle, as done by the other devi-
ces. Table 9–16 shows the 4 word burst sequencing of standard SBSRAMs in
linear burst mode. In order to avoid the SBSRAM wrapping around to an unin-
tended address (indicated in gray), the 'C6211/C6711 strobes a new address
into the SBSRAM. This is also done if random reads are done or if the burst
order should be non-incrementing or reverse order burst.
SBSRAM Address
EMIF Address
First address
Fourth Address
Case 1 Case 2
A[1:0] A[1:0]
EA[3:2] EA[3:2]
00 01
01 10
10 11
11 00
External Memory Interface
SBSRAM Interface
Case 3 Case 4
A[1:0] A[1:0]
EA[3:2] EA[3:2]
10 11
11 00
00 01
01 10
9-43