L1D 2-Way Set Associative Cache Diagram - Texas Instruments TMS320C6201 Reference Manual

Figure 4–9. L1D 2–Way Set Associative Cache Diagram.
Way 1
Way 0
Tag Set
Address
Tag RAM
Data out
=
Address
Tag RAM
Data out
=
Subline Word Offset
Address
Cache
data
Data out
Address
Cache
data
Data out
TMS320C6211/C6711 Two-Level Internal Memory
L1D Description
L2
Data
0 1
1 0
256
64
32
Data
4-11