Texas Instruments TMS320C6201 Reference Manual page 197

Overview
The I/O port has two modes of operation, which can coexist in a single system:
asynchronous I/O mode and synchronous FIFO mode. These modes are
selectable for each of expansion bus's four XCE spaces. The first mode
(asynchronous I/O mode) provides output strobes, which are highly
programmable like the asynchronous signals of the external memory interface
(EMIF). The expansion bus interface provides four output address signals in
this mode, with external decode this provides for up to 16 devices per XCE
space. The FIFO mode provides a glueless interface to a single synchronous
read FIFO, or up to four synchronous write FIFOs. With a minimal amount of
glue, this can be extended to up to 16 read and 16 write FIFOs per XCE space.
Connectivity of the expansion bus I/O port and DSP memory is provided
through the DMA controller.
The second sub-block of the expansion bus consists of the host port interface.
This interface can operate in one of two modes: synchronous and asynchro-
nous. The synchronous mode offers master and slave functionality, and has
multiplexed address and data signals. The asynchronous mode is slave only,
and is similar to the HPI on the 'C6201/C6211/C6701/C6711, but is extended
to a 32-bit data path. The asynchronous host port mode is used to interface
to microprocessors which utilize an asynchronous bus.
Connectivity of the expansion bus host port interface and the DSP memory
space is provided by the DMA auxiliary port. Dedicated address and data reg-
isters connect the host port interface to the expansion bus host channel. An
external master accesses these registers using external data and interface
control signals. Through a dedicated port the DMA provides connectivity be-
tween the processor and the expansion bus I/O port. To initiate transfers via
the synchronous host port interface, the CPU has to configure a set of regis-
ters. Figure 8–2 shows a chip-level block diagram.
Expansion Bus 8-3