Internal Program Ram Address Mapping In Cache Mode; Cache Operation - Texas Instruments TMS320C6201 Reference Manual

3.3 Cache Operation

Table 3–4. Internal Program RAM Address Mapping in Cache Mode
Block 0
When the PCC field of the CPU Control Status Register is programmed for one
of the Cache modes, block 1 operates as a cache while block 0 remains
mapped into internal program space. Table 3–4 shows the addresses occu-
pied by the RAM that is not used for cache, for each Map Mode.
Map 0
0140 0000h – 0141 FFFFh
The cache on the C6202 operates identically to the C6201 cache. Any CPU
or DMA access to the memory range that was occupied by the cache RAM
returns undefined results. As in mapped mode, simultaneous accesses to
block 0 by the CPU and DMA stalls the DMA until the CPU has completed its
access. A DMA access to block 0 while the cache is flushed continues without
stalling. The CPU is halted during a cache flush. You must ensure that all DMA
accesses to block 1 have completed before the cache is enabled.
Note:
If you change the operation mode of the PMEMC, you should use the follow-
ing assembly routine to ensure correct operation of the PMEMC. This routine
enables the cache. To change the PMEMC operation mode to a state other
than cache enable, you should modify line four of the routine to correspond
the the value of PCC that you want moved into B5. For example, to put the
cache into mapped mode 0000h should be moved into B5. The CPU regis-
ters used in this example have no significance. Any of the registers A0–A15
or B0–B15 can be used in the program.
.align 32
MVC .S2 CSR,B5
|| MVK .S1 0xff1f,A5
AND .L1x A5,B5,A5
|| MVK S2 0x0040,B5 ;set cache enable mask
OR .L2x A5,B5,B5
MVC .S2 B5,CSR
NOP 4
NOP
Map 1
0000 0000h – 0001 FFFFh
;copy control status register
;clear PCC field of CSR value
;set cache enable bit
;update CSR to enable cache
TMS320C6202 Program and Data Memory
Cache Operation
3-5