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SDRAM Interface
9.4.5
Address Shift
Table 9–13. TMS320C6201/C6202/C6701 Byte Address to EA Mapping for
SDRAM RAS and CAS
EMIF
Pins
SDRAM
SDRAM
Pins
Width
SDWID
x16
1
Address
bit
bit
Address
x8
0
bit
bit
Legend:
Bit is internally latched during an ACTV command.
Reserved for future use. Undefined.
Note:
The RAS and CAS values indicate the bit of the byte address present on the corresponding EA pin during a RAS or CAS
cycle.
9-32
Because the same EMIF pins determine the row and column address, the
EMIF interface appropriately shifts the address in row and column address
selection. Table 9–13 and shows the translation between bits of the byte ad-
dress and how they appear on the EA pins for row and column addresses.
SDRAMs use the address inputs for control as well as address.
The following factors apply to the address shifting process for the
'C6201/C6202/C6701:
The address line that corresponds to the SDRAM's bank select field (A11
on 16M-bit SDRAM; A13 and A12 on 64M-bit SDRAM) is latched internally
by the SDRAM controller. This ensures that the bank select remains correct
during READ and WRT commands. Thus, the EMIF maintains these values
as shown in both row and column addresses.
The EMIF forces SDA10 to be low when RAS is not active and high during
DCAB commands at the end of a page of accesses. This prevents the au-
toprecharge from occurring following a READ or WRT command.
The following factors apply to the address shifting process for the
'C6211/C6711:
The address shift is controlled completely by the column size field
(SDCSZ), and is unaffected by the bank and row size fields. The bank and
row size are used internally to determine whether a page is opened
EA12 is connected directly to A10 signal, instead of using a dedicated pre-
charge pin SDA10.
E
E
E
A
A
A
[21:17]
16
15
A
DRAM
13
Cmd
RAS
23
CAS
23
RAS
CAS
S
E
E
E
E
D
A
A
A
A
A
14
13
11
10
10
A
A
A
A
A
12
11
10
9
8
22
21
20
19
18
17
22
21
20
19
18
23
22
21
20
19
18
23
22
21
20
10
E
E
E
E
E
E
A
A
A
A
A
A
9
8
7
6
5
4
A
A
A
A
A
A
7
6
5
4
3
2
16
15
14
13
12
9
8
7
6
5
4
17
16
15
14
13
9
8
7
6
5
4
E
E
A
A
3
2
A
A
1
0
11
10
3
2
12
11
3
2
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