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Reference Manual
High-Performance Fixed-Point Digital
D
Signal Processor (DSP) TMS320C6201
- - 5-ns Instruction Cycle Time
- - 200-MHz Clock Rate
- - Eight 32-Bit Instructions/Cycle
- - 1600 MIPS
VelociTI™ Advanced Very Long Instruction
D
Word (VLIW) TMS320C62x™ DSP CPU Core
- - Eight Independent Functional Units:
- - Six ALUs (32-/40-Bit)
- - Two 16-Bit Multipliers (32-Bit Results)
- - Load-Store Architecture With 32 32-Bit
General-Purpose Registers
- - Instruction Packing Reduces Code Size
- - All Instructions Conditional
Instruction Set Features
D
- - Byte-Addressable (8-, 16-, 32-Bit Data)
- - 32-Bit Address Range
- - 8-Bit Overflow Protection
- - Saturation
- - Bit-Field Extract, Set, Clear
- - Bit-Counting
- - Normalization
1M-Bit On-Chip SRAM
D
- - 512K-Bit Internal Program/Cache
(16K 32-Bit Instructions)
- - 512K-Bit Dual-Access Internal Data
(64K Bytes) Organized as Two Blocks for
Improved Concurrency
32-Bit External Memory Interface (EMIF)
D
- - Glueless Interface to Asynchronous
Memories: SRAM and EPROM
- - Glueless Interface to Synchronous
Memories: SDRAM and SBSRAM
Four-Channel Bootloading
D
Direct-Memory-Access (DMA) Controller
with an Auxiliary Channel
16-Bit Host-Port Interface (HPI)
D
- - Access to Entire Memory Map
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
VelociTI and TMS320C62x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
All other trademarks are the property of their respective owners.
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
FIXED-POINT DIGITAL SIGNAL PROCESSOR
D
D
D
D
D
D
D
D
•
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251--1443
SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004
GJC/GJL
352-PIN BALL GRID ARRAY (BGA) PACKAGES
(BOTTOM VIEW)
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11
13
15
2
4
6
8
10
12
14
Two Multichannel Buffered Serial Ports
(McBSPs)
- - Direct Interface to T1/E1, MVIP, SCSA
Framers
- - ST-Bus-Switching Compatible
- - Up to 256 Channels Each
- - AC97-Compatible
- - Serial Peripheral Interface (SPI)
Compatible (Motorola™)
Two 32-Bit General-Purpose Timers
Flexible Phase-Locked Loop (PLL) Clock
Generator
†
IEEE-1149.1 (JTAG
) Boundary-Scan
Compatible
352-Pin BGA Package (GJC Suffix)
352-Pin BGA Package (GJL Suffix)
CMOS Technology
- - 0.18-μm/5-Level Metal Process
3.3-V I/Os, 1.8-V Internal
Copyright © 2004, Texas Instruments Incorporated
TMS320C6201
17
19 21
23
25
16
18
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24
26
1
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Summary of Contents for Texas Instruments TMS320C6201
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Page 1: Gjc/Gjl Bga Packages (Bottom View)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. VelociTI and TMS320C62x are trademarks of Texas Instruments. -
Page 2: Table Of Contents
TMS320C6000 and C62x are trademarks of Texas Instruments. Windows is a registered trademark of the Microsoft Corporation. † The TMS320C6201 device shall be referred to as C6201 throughout the remainder of this document. • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443... -
Page 3: Device Characteristics
Advance Information (AI) Production Data (PD) TMS320C6201GJC200 (For more details on the C6000™ DSP part TMS320C6201GJCA200 Device Part Numbers numbering, see Figure 4) TMS320C6201GJL200 TMS320C6201GJLA200 C6000 is a trademark of Texas Instruments. • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443... -
Page 4: Functional And Cpu (Dsp Core) Block Diagram
TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 functional and CPU (DSP core) block diagram C6201 Digital Signal Processors SDRAM SBSRAM Program Internal Program Memory Access/Cache SRAM (64K Bytes) External Memory Controller ROM/FLASH Interface (EMIF) -
Page 5: Cpu (Dsp Core) Description
TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 CPU (DSP core) description The CPU fetches VelociTI™ advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI™ VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. - Page 6 TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 CPU (DSP core) description (continued) src1 src2 long dst long src long src long dst Register Data Path A File A src1 (A0- -A15) src2 src1 src2...
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Page 7: Signal Groups Description
TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 signal groups description CLKIN BOOTMODE4 CLKOUT2 BOOTMODE3 Boot Mode CLKOUT1 BOOTMODE2 CLKMODE1 BOOTMODE1 CLKMODE0 BOOTMODE0 PLLFREQ3 Clock/PLL PLLFREQ2 PLLFREQ1 RESET PLLV PLLG EXT_INT7 PLLF EXT_INT6 EXT_INT5 Reset and... - Page 8 TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 signal groups description (continued) ED[31:0] Data Asynchronous Memory Control ARDY Memory Map Space Select SSADS SBSRAM SSOE EA[21:2] Control Word Address SSWE SSCLK SDA10 Byte Enables SDRAS...
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Page 9: Signal Descriptions
TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 Signal Descriptions PIN NO. SIGNAL SIGNAL † † TYPE TYPE DESCRIPTION DESCRIPTION NAME CLOCK/PLL CLKIN Clock Input CLKOUT1 AF22 AC18 Clock output at full device speed CLKOUT2... - Page 10 TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 Signal Descriptions (Continued) PIN NO. SIGNAL SIGNAL † † TYPE TYPE DESCRIPTION DESCRIPTION NAME HOST-PORT INTERFACE (HPI) HINT Host interrupt (from DSP to host) HCNTL1 Host control -- selects between control, address, or data registers...
- Page 11 TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 Signal Descriptions (Continued) PIN NO. SIGNAL SIGNAL † † TYPE TYPE DESCRIPTION DESCRIPTION NAME EMIF - - CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY AE22 AD20...
- Page 12 TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 Signal Descriptions (Continued) PIN NO. SIGNAL SIGNAL † † TYPE TYPE DESCRIPTION DESCRIPTION NAME EMIF - - DATA ED31 ED30 ED29 ED28 ED27 ED26 ED25 ED24 ED23...
- Page 13 TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 Signal Descriptions (Continued) PIN NO. SIGNAL SIGNAL † † TYPE TYPE DESCRIPTION DESCRIPTION NAME EMIF - - SYNCHRONOUS BURST SRAM (SBSRAM) CONTROL SSADS AC20 AD19 SBSRAM address strobe...
- Page 14 TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 Signal Descriptions (Continued) PIN NO. SIGNAL SIGNAL † † TYPE TYPE DESCRIPTION DESCRIPTION NAME MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0) CLKS0 External clock source (as opposed to internal)
- Page 15 TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 Signal Descriptions (Continued) PIN NO. SIGNAL SIGNAL † † TYPE TYPE DESCRIPTION DESCRIPTION NAME 3.3-V SUPPLY VOLTAGE PINS 3 3 V supply voltage 3.3-V supply voltage AB26...
- Page 16 TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 Signal Descriptions (Continued) PIN NO. SIGNAL SIGNAL † † TYPE TYPE DESCRIPTION DESCRIPTION NAME 1.8-V SUPPLY VOLTAGE PINS 1 8 V supply voltage 1.8-V supply voltage AB23...
- Page 17 TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 Signal Descriptions (Continued) PIN NO. SIGNAL SIGNAL † † TYPE TYPE DESCRIPTION DESCRIPTION NAME 1.8-V SUPPLY VOLTAGE PINS (CONTINUED) AD23 AC12 AD24 AC13 AD25 AC18 AD26 AC23 1 8 V supply voltage 1.8-V supply voltage...
- Page 18 TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 Signal Descriptions (Continued) PIN NO. SIGNAL SIGNAL † † TYPE TYPE DESCRIPTION DESCRIPTION NAME GROUND PINS (CONTINUED) Ground pins Ground pins AA23 AB23 AA23 AC14 AB24 AC16...
- Page 19 TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 Signal Descriptions (Continued) PIN NO. SIGNAL SIGNAL † † TYPE TYPE DESCRIPTION DESCRIPTION NAME GROUND PINS (CONTINUED) AD25 AC26 AD22 AE13 AE13 AE14 AE16 AE23 AE19 AE23...
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Page 20: Development Support
TMS320™ DSP documentation or any TMS320™ DSP support products from Texas Instruments. An additional document, the TMS320 Third-Party Support Reference Guide (SPRU052), contains information about TMS320™ DSP-related products from other companies in the industry. - Page 21 DSP devices and support tools. Each TMS320 DSP commerical family member has one of three prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).
- Page 22 C6000 DSP: 6201 6204 6701 6202 6205 6711 6202B 6211 6712 6203 † BGA = Ball Grid Array Figure 4. TMS320C6000 Device Nomenclature (Including TMS320C6201) MicroStar BGA is a trademark of Texas Instruments. • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443...
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Page 23: Documentation Support
The tools support documentation is electronically available within the Code Composer Studio™ IDE. For a complete listing of the latest C6000™ DSP documentation, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). -
Page 24: Clock Pll
TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 clock PLL All of the C62x clocks are generated from a single source through the CLKIN pin. This source clock either drives the PLL, which generates the internal CPU clock, or bypasses the PLL to become the CPU clock. -
Page 25: Power-Down Mode Logic
TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 clock PLL (continued) Table 2. PLL Component Selection Table CPU CLOCK CLKIN CLKOUT2 TYPICAL FREQUENCY CLKMODE RANGE RANGE LOCK TIME (CLKOUT1) (Ω) (nF) (pF) † (MHz) (MHz) (μs) - Page 26 TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 Enable or Enabled Non-Enabled Reserved Interrupt Wake Interrupt Wake R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Legend: R/W--x = Read/write reset value NOTE: The shadowed bits are not part of the power-down logic discussion and therefore are not covered here. For information on these other bit fields in the CSR register, see the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189).
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Page 27: Power-Supply Sequencing
TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 Table 3. Characteristics of the Power-Down Modes PRWD FIELD POWER-DOWN WAKE-UP METHOD EFFECT ON CHIP’S OPERATION (BITS 15- -10) MODE 000000 No power-down — — CPU halted (except for the interrupt logic) -
Page 28: Absolute Maximum Ratings Over Operating Case Temperature Ranges
TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize inductance and resistance in the power delivery path. Additionally, when designing for high-performance applications utilizing the C6000 platform of DSPs, the PC board should include separate power planes for core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors. -
Page 29: Electrical Characteristics Over Recommended Ranges Of Supply Voltage And Operating Case Temperature
TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted) PARAMETER TEST CONDITIONS UNIT = MIN, High-level output voltage = MAX = MIN,... -
Page 30: Parameter Measurement Information
TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 PARAMETER MEASUREMENT INFORMATION Tester Pin Electronics Output 50 Ω Under comm Test † Where: = 2 mA = 2 mA = 0.8 V comm = 15--30-pF typical load-circuit capacitance †... -
Page 31: Input And Output Clocks
TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 INPUT AND OUTPUT CLOCKS †‡ timing requirements for CLKIN (see Figure 11) - -200 CLKMODE CLKMODE UNIT = x4 = x1 Cycle time, CLKIN c(CLKIN) Pulse duration, CLKIN high 0.4C... - Page 32 TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 INPUT AND OUTPUT CLOCKS (CONTINUED) †‡ switching characteristics over recommended operating conditions for CLKOUT2 (see Figure 13) - -200 UNIT UNIT Cycle time, CLKOUT2 2P -- 0.7 2P + 0.7...
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Page 33: Asynchronous Memory Timing
TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 ASYNCHRONOUS MEMORY TIMING † timing requirements for asynchronous memory cycles (see Figure 15 and Figure 16) - -200 UNIT UNIT Setup time, read EDx valid before CLKOUT1 high... - Page 34 TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 ASYNCHRONOUS MEMORY TIMING (CONTINUED) Not ready = 2 Setup = 2 Strobe = 5 HOLD = 1 CLKOUT1 BE[3:0] EA[21:2] ED[31:0] ARDY Figure 15. Asynchronous Memory Read Timing...
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Page 35: Synchronous-Burst Memory Timing
TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 SYNCHRONOUS-BURST MEMORY TIMING timing requirements for synchronous-burst SRAM cycles (full-rate SSCLK) (see Figure 17) - -200 UNIT UNIT Setup time, read EDx valid before SSCLK high su(EDV-SSCLKH) - Page 36 TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED) SSCLK BE[3:0] EA[21:2] ED[31:0] SSADS SSOE SSWE Figure 17. SBSRAM Read Timing (Full-Rate SSCLK) SSCLK BE[3:0] EA[21:2] ED[31:0] SSADS SSOE SSWE Figure 18. SBSRAM Write Timing (Full-Rate SSCLK) •...
- Page 37 TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED) timing requirements for synchronous-burst SRAM cycles (half-rate SSCLK) (see Figure 19) - -200 UNIT UNIT Setup time, read EDx valid before SSCLK high...
- Page 38 TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED) SSCLK BE[3:0] EA[21:2] ED[31:0] SSADS SSOE SSWE Figure 19. SBSRAM Read Timing (1/2 Rate SSCLK) SSCLK BE[3:0] EA[21:2] ED[31:0] SSADS SSOE SSWE Figure 20. SBSRAM Write Timing (1/2 Rate SSCLK) •...
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Page 39: Synchronous Dram Timing
TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 SYNCHRONOUS DRAM TIMING timing requirements for synchronous DRAM cycles (see Figure 21) - -200 UNIT UNIT Setup time, read EDx valid before SDCLK high su(EDV-SDCLKH) Hold time, read EDx valid after SDCLK high... - Page 40 TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 SYNCHRONOUS DRAM TIMING (CONTINUED) READ READ READ SDCLK BE[3:0] EA[15:2] ED[31:0] SDA10 SDRAS SDCAS SDWE Figure 21. Three SDRAM Read Commands WRITE WRITE WRITE SDCLK BE[3:0] EA[15:2]...
- Page 41 TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 SYNCHRONOUS DRAM TIMING (CONTINUED) ACTV SDCLK BE[3:0] Bank Activate/Row Address EA[15:2] ED[31:0] Row Address SDA10 SDRAS SDCAS SDWE Figure 23. SDRAM ACTV Command DCAB SDCLK BE[3:0] EA[15:2]...
- Page 42 TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 SYNCHRONOUS DRAM TIMING (CONTINUED) REFR SDCLK BE[3:0] EA[15:2] ED[31:0] SDA10 SDRAS SDCAS SDWE Figure 25. SDRAM REFR Command SDCLK BE[3:0] EA[15:2] MRS Value ED[31:0] SDA10 SDRAS SDCAS SDWE Figure 26.
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Page 43: Hold/Holda Timing
TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 HOLD/HOLDA TIMING † timing requirements for the HOLD/HOLDA cycles (see Figure 27) - -200 UNIT UNIT Setup time, HOLD high before CLKOUT1 high su(HOLDH-CKO1H) Hold time, HOLD low after CLKOUT1 high h(CKO1H-HOLDL) †... -
Page 44: Reset Timing
TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 RESET TIMING timing requirements for reset (see Figure 28) - -200 UNIT UNIT CLKOUT1 † Width of the RESET pulse (PLL stable) cycles w(RST) w(RST) ‡ Width of the RESET pulse (PLL needs to sync up) μs... - Page 45 TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 RESET TIMING (CONTINUED) CLKOUT1 RESET CLKOUT2 SDCLK SSCLK †‡ LOW GROUP †‡ HIGH GROUP †‡ Z GROUP † Low group consists of: IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1...
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Page 46: External Interrupt Timing
TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 EXTERNAL INTERRUPT TIMING †‡ timing requirements for interrupt response cycles (see Figure 29) - -200 UNIT UNIT Width of the interrupt pulse low w(ILOW) Width of the interrupt pulse high w(IHIGH) †... -
Page 47: Host-Port Interface Timing
TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 HOST-PORT INTERFACE TIMING †‡ timing requirements for host-port interface cycles (see Figure 30, Figure 31, Figure 32, and Figure 33) - -200 UNIT UNIT § Setup time, select signals... - Page 48 TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 HOST-PORT INTERFACE TIMING (CONTINUED) HCNTL[1:0] HR/W HHWIL † HSTROBE HD[15:0] (output) 1st Half-Word 2nd Half-Word HRDY (case 1) HRDY (case 2) † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
- Page 49 TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 HOST-PORT INTERFACE TIMING (CONTINUED) HCNTL[1:0] HBE[1:0] HR/W HHWIL † HSTROBE HD[15:0] (input) 1st Half-Word 2nd Half-Word HRDY † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
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Page 50: Multichannel Buffered Serial Port Timing
TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING †‡ timing requirements for McBSP (see Figure 34) - -200 UNIT UNIT § Cycle time, CLKR/X CLKR/X ext c(CKRX) ¶ Pulse duration, CLKR/X high or CLKR/X low... - Page 51 TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) †‡§ switching characteristics over recommended operating conditions for McBSP (see Figure 34) - -200 PARAMETER PARAMETER UNIT UNIT Delay time, CLKS high to CLKR/X high for internal CLKR/X...
- Page 52 TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKS CLKR FSR (int) FSR (ext) Bit(n-1) (n-2) (n-3) CLKX FSX (int) FSX (ext) FSX (XDATDLY=00b) Bit 0 Bit(n-1) (n-2) (n-3) Figure 34.
- Page 53 TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for FSR when GSYNC = 1 (see Figure 35) - -200 UNIT UNIT Setup time, FSR high before CLKS high...
- Page 54 TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) †‡ timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0 (see Figure 36) - -200...
- Page 55 TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKX Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Figure 36. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 •...
- Page 56 TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) †‡ timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0 (see Figure 37) - -200...
- Page 57 TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKX Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Figure 37. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 •...
- Page 58 TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) †‡ timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1 (see Figure 38) - -200...
- Page 59 TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) †‡ timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1 (see Figure 39) - -200...
- Page 60 TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKX Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Figure 39. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 •...
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Page 61: Dmac, Timer, Power-Down Timing
TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 DMAC, TIMER, POWER-DOWN TIMING switching characteristics over recommended operating conditions for DMAC outputs (see Figure 40) - -200 PARAMETER PARAMETER UNIT UNIT Delay time, CLKOUT1 high to DMAC valid... -
Page 62: Jtag Test-Port Timing
TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 JTAG TEST-PORT TIMING timing requirements for JTAG test port (see Figure 43) - -200 UNIT UNIT Cycle time, TCK c(TCK) Setup time, TDI/TMS/TRST valid before TCK high... -
Page 63: Revision History
TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 REVISION HISTORY This data sheet revision history highlights the technical changes made to the SPR051G device-specific data sheet to make it an SPRS051H revision. Scope: Applicable updates to the C62x device family, specifically relating to the C6201 device, have been incor- porated. -
Page 64: Thermal/Mechanical Data
TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 THERMAL/MECHANICAL DATA The mechanical package diagrams that follow the tables reflect the most current released mechanical data available for the designated devices. thermal resistance characteristics for GJC-352 package (S-PBGA package) †... - Page 65 PACKAGE OPTION ADDENDUM www.ti.com 25-Oct-2016 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples Drawing (4/5) TMS320C6201GGP167 OBSOLETE Call TI Call TI 0 to 0 TMS320C6201GGP200 OBSOLETE Call TI Call TI...
- Page 66 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TMS320C6201 :...
- Page 67 MECHANICAL DATA MPBG018A – OCTOBER 1996 – REVISED JANUARY 2002 GGP (S-PBGA-N352) PLASTIC BALL GRID ARRAY (CAVITY DOWN) 35,20 31,75 TYP 34,80 1,27 0,50 MIN 0,635 A1 Corner 13 15 Bottom View 0,91 NOM 1,70 MAX Seating Plane 0,90 0,15 0,10 0,50 0,60...
- Page 68 MECHANICAL DATA MPBG067B – SEPTEMBER 1998 – REVISED JANUARY 2002 GJC (S-PBGA-N352) PLASTIC BALL GRID ARRAY 35,20 34,80 33,20 31,75 TYP 32,80 1,27 21,00 NOM 0,635 19 21 A1 Corner Bottom View Heat Slug See Note E 3,50 MAX 1,00 NOM Seating Plane 0,90 ∅...
- Page 69 MECHANICAL DATA MPBG069D – SEPTEMBER 1998 – REVISED MARCH 2002 GJL (S-PBGA-N352) PLASTIC BALL GRID ARRAY 27,20 26,80 25,20 25,00 TYP 24,80 1,00 16,30 NOM 0,50 A1 Corner 11 13 15 17 19 21 23 25 12 14 Bottom View Heat Slug See Note E 3,80 MAX...
- Page 70 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue.
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