Dma Channel Condition Descriptions - Texas Instruments TMS320C6201 Reference Manual

DMA Channel Condition Determination
5.10.1 Definition of Channel Conditions
Table 5–10. DMA Channel Condition Descriptions
Bitfield Event
SX Split transmit overrun
receive
FRAME Frame complete
LAST Last frame
WDROP Dropped read/write
synchronization
RDROP
BLOCK Block transfer
finished
5-34
Table 5–10 describes each of the condition flags in the DMA channel second-
ary control register.
Depending on the system application, these conditions can represent errors.
The last frame condition can be used to change the reload register values for
autoinitialization. The frame index and element count reload are used every
frame. Thus, you must wait to change these values until all but the last frame
transfer in a block transfer finishes. Otherwise, the current block transfer is af-
fected.
Occurs if
The split operation is enabled
and transmit element transfers
get seven or more element
transfers ahead of receive ele-
ment transfers
After the last write transfer in
each frame is written to
memory
After all counter adjustments
for the next-to-last frame in a
block transfer finish
A subsequent synchronization
event occurs before the last
one is cleared
After the last write transfer in
a block transfer is written to
memory
COND Cleared By
If IE Enabled Otherwise
A user write of 0 to COND
A user write of 0 Two CPU clocks
to COND later
A user write of 0 Two CPU clocks
to COND later
A user write of 0 to COND
A user write of 0 Two CPU clocks
to COND later