Channel Chain Enable Register (Ccer) - Texas Instruments TMS320C6201 Reference Manual

Figure 6–16. Channel Chain Enable Register (CCER)
31 12
rsvd
R, +0
11 10
CCE11 CCE10
RW, +0 RW, +0
For example, if TCC = 1000b and CCER[8] = 1 is specified for EDMA channel
4, an external interrupt on EXT_INT4 initiates the EDMA transfer. Once
channel 4 transfer is complete, the EDMA controller initiates (TCINT = 1) the
next transfer specified by EDMA channel 8. This is because TCC = 1000b
(channel 4 transfer completion code) is the sync event for EDMA channel 8.
The corresponding CIPR bit 8 is set after channel 4 completes and generates
an EDMA_INT (provided CIER[8] = 1) to the CPU. If the CPU interrupt is not
desired, the corresponding interrupt enable bit, CIER[8] must be set to '0'. If
channel 8 transfer is not desired, CCER[8] must be set to '0'.
9 8
CCE9 CCE8
RW, +0 RW, +0
EDMA Controller
EDMA Interrupt Generation
7 0
rsvd
R, +0
6-35