Figure 11–10. Single-Phase Frame of Four 8-Bit Elements
Element 1
CLKR
FSR
DR
RBR–to–DRR copy
CLKX
FSX
DX
DXR-to-XSR copy
Figure 11–11.Single-Phase Frame of One 32-Bit Element
CLKR
FSR
DR
CLKX
FSX
DX
Element 2
RBR-to-DRR copy
DXR-to-XSR copy
The example in Figure 11–10 can also be viewed as a data stream of a single-
phase frame of one 32-bit data element, as shown in Figure 11–11. In this
case:
(R/X)PHASE = 0, indicating a single phase frame
(R/X)FRLEN1 = 0b, indicating a 1-element frame
(R/X)WDLEN1 = 101b, indicating 32-bit elements
In this situation, one 32-bit data element is transferred to and from the McBSP
by the CPU or the DMA controller. Thus, one read of DRR and one write of DXR
is necessary for each frame. As a result, the number of transfers is one fourth
that of the previous case. This manipulation reduces the percentage of bus
time required for serial port data movement.
Data Transmission and Reception
Element 3
RBR–to-DRR copy
DXR-to-XSR copy
Element 1
Multichannel Buffered Serial Ports
Element 4
RBR-to-DRR copy
DXR-to-XSR copy
RBR to DRR copy
DXR to XSR Copy
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