Texas Instruments TMS320C642X User Manual
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Texas Instruments TMS320C642X User Manual

Texas Instruments TMS320C642X User Manual

Dsp inter-integrated circuit (i2c) peripheral
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TMS320C642x DSP
Inter-Integrated Circuit (I2C) Peripheral
User's Guide
Literature Number: SPRUEN0D
March 2011

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Summary of Contents for Texas Instruments TMS320C642X

  • Page 1 TMS320C642x DSP Inter-Integrated Circuit (I2C) Peripheral User's Guide Literature Number: SPRUEN0D March 2011...
  • Page 2 SPRUEN0D – March 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...

  • Page 3: Table Of Contents

    I2C Extended Mode Register (ICEMDR) 3.12 I2C Prescaler Register (ICPSC) 3.13 I2C Peripheral Identification Register (ICPID1) 3.14 I2C Peripheral Identification Register (ICPID2) Appendix A Revision History SPRUEN0D – March 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated Table of Contents...
  • Page 4 I2C Extended Mode Register (ICEMDR) I2C Prescaler Register (ICPSC) I2C Peripheral Identification Register 1 (ICPID1) I2C Peripheral Identification Register 2 (ICPID2) List of Figures List of Figures © 2011, Texas Instruments Incorporated www.ti.com SPRUEN0D – March 2011 Submit Documentation Feedback...
  • Page 5 I2C Prescaler Register (ICPSC) Field Descriptions I2C Peripheral Identification Register 1 (ICPID1) Field Descriptions I2C Peripheral Identification Register 2 (ICPID2) Field Descriptions Document Revision History SPRUEN0D – March 2011 Submit Documentation Feedback List of Tables © 2011, Texas Instruments Incorporated List of Tables...

  • Page 6: Preface

    About This Manual This document describes the inter-integrated circuit (I2C) peripheral in the TMS320C642x Digital Signal Processor (DSP). The I2C peripheral provides an interface between the DSP and other devices that are compliant with Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1 and connected by way of an I2C-bus.

  • Page 7: Introduction

    Semiconductors Inter-IC bus (I2C-bus) specification version 2.1. Purpose of the Peripheral The I2C peripheral provides an interface between the TMS320C642x DSP and other devices that are compliant with the I2C-bus specification and connected by way of an I2C-bus. External components that are attached to this two-wire serial bus can transmit and receive data that is up to eight bits wide both to and from the DSP through the I2C peripheral.

  • Page 8: Functional Block Diagram

    ICDRR Control/status registers Clock synchronizer Prescaler Noise filters I2C INT ICREVT Arbitrator ICXEVT © 2011, Texas Instruments Incorporated www.ti.com Section 2 for detailed information Peripheral data bus EDMA Interrupt to CPU Sync events to EDMA controller SPRUEN0D – March 2011...

  • Page 9: Peripheral Architecture

    Figure Figure 2. Multiple I2C Modules Connected Pull-up resistors Serial data (SDA) Serial clock (SCL) SPRUEN0D – March 2011 Submit Documentation Feedback TI device EPROM © 2011, Texas Instruments Incorporated Peripheral Architecture controller TI device Inter-Integrated Circuit (I2C) Peripheral...

  • Page 10: Clock Generation

    (ICCL + d) + (ICCH + d) Where d depends on IPSC value in ICPSC: To I2C bus IPSC value 2h−FFh CAUTION © 2011, Texas Instruments Incorporated www.ti.com I2C module I2C input clock frequency (IPSC + 1) SPRUEN0D – March 2011...

  • Page 11: Clock Synchronization

    (high) are not fixed and depend on the associated power supply level. See the device-specific data manual for more information. SPRUEN0D – March 2011 Submit Documentation Feedback Figure 4 illustrates the clock synchronization. The wired-AND property of Wait state © 2011, Texas Instruments Incorporated Peripheral Architecture Start HIGH period Inter-Integrated Circuit (I2C) Peripheral...

  • Page 12: Start And Stop Conditions

    Figure 5. Bit Transfer on the I2C-Bus Data line stable data Change of data allowed Figure Section 3.9 © 2011, Texas Instruments Incorporated www.ti.com Figure 5). The high or low state for a description of ICMDR STOP condition (P) SPRUEN0D – March 2011...

  • Page 13: Serial Data Formats

    Figure 7. I2C Peripheral Data Transfer Acknowledgement bit from slave R/W ACK (Figure 8), the first byte after a START condition (S) consists of a 7-bit slave Data © 2011, Texas Instruments Incorporated Peripheral Architecture (No-)Acknowledgement bit from receiver STOP condition (P) Data...

  • Page 14: I2C Peripheral 10-Bit Addressing Format With Master-Transmitter Writing To Slave-Receiver (Fdf = 0, Xa = 1 In Icmdr)

    10), the first bits after a START condition (S) are a data word. An ACK bit is Data (FDF = 0, XA = 0 in ICMDR) Data Slave address number © 2011, Texas Instruments Incorporated www.ti.com Data Data ACK P Figure 11.

  • Page 15: Endianness Considerations

    I2C peripheral on SCL. The clock pulses are inhibited and SCL is held low when the intervention of the processor is required (XSMT = 0 in ICSTR) after data has been transmitted. SPRUEN0D – March 2011 Submit Documentation Feedback Inter-Integrated Circuit (I2C) Peripheral © 2011, Texas Instruments Incorporated Peripheral Architecture...

  • Page 16: Nack Bit Generation

    Set the NACKMOD bit of ICMDR before the rising edge of the last data bit you intend to receive. © 2011, Texas Instruments Incorporated www.ti.com SPRUEN0D – March 2011 Submit Documentation Feedback...

  • Page 17: 2.10 Arbitration

    Data from device #2 Bus line SPRUEN0D – March 2011 Submit Documentation Feedback illustrates the arbitration procedure between two devices. The first Device #1 lost arbitration and switches off Inter-Integrated Circuit (I2C) Peripheral © 2011, Texas Instruments Incorporated Peripheral Architecture...

  • Page 18: 2.11 Reset Considerations

    Once the bus is determined to be available (the bus is not busy), the I2C is ready to proceed with the desired communication. Inter-Integrated Circuit (I2C) Peripheral © 2011, Texas Instruments Incorporated www.ti.com SPRUEN0D – March 2011...
  • Page 19 CPU is used to move data from the I2C receive register to CPU memory (memory accessible by the CPU). 1. Enable I2C clock from the Power and Sleep Controller (see the TMS320C642x DSP Power and Sleep Controller (PSC) User's Guide (SPRUEN8)).
  • Page 20 Wait for Transmit Interrupt to be received, ICXRDY = 1. 14. Perform step 13 until a STOP condition is detected (SCD = 1). Inter-Integrated Circuit (I2C) Peripheral Table 15 (No Activity case). © 2011, Texas Instruments Incorporated www.ti.com SPRUEN0D – March 2011 Submit Documentation Feedback...

  • Page 21: 2.13 Interrupt Support

    Controller (PSC). The PSC acts as a master controller for power management for all of the peripherals on the device. For detailed information on power management procedures using the PSC, see the TMS320C642x DSP Power and Sleep Controller (PSC) User's Guide (SPRUEN8). SPRUEN0D – March 2011...

  • Page 22: 2.16 Emulation Considerations

    I2C Data Transmit Register I2C Mode Register I2C Interrupt Vector Register I2C Extended Mode Register I2C Prescaler Register I2C Peripheral Identification Register 1 I2C Peripheral Identification Register 2 © 2011, Texas Instruments Incorporated www.ti.com Section 3.9). Section Section 3.1 Section 3.2 Section 3.3...

  • Page 23: I2C Own Address Register (Icoar)

    In 10-bit addressing mode (XA = 1 in ICMDR): bits 9-0 provide the 10-bit slave address of the I2C. SPRUEN0D – March 2011 Submit Documentation Feedback Figure 13 and described in Figure 13. I2C Own Address Register (ICOAR) Reserved © 2011, Texas Instruments Incorporated Registers Table OADDR R/W-0 Inter-Integrated Circuit (I2C) Peripheral...

  • Page 24: I2C Interrupt Mask Register (Icimr)

    Interrupt request is disabled. Interrupt request is enabled. Inter-Integrated Circuit (I2C) Peripheral Figure 14 and described Reserved ICXRDY ICRRDY ARDY R/W-0 R/W-0 R/W-0 © 2011, Texas Instruments Incorporated www.ti.com Table NACK R/W-0 R/W-0 SPRUEN0D – March 2011 Submit Documentation Feedback...

  • Page 25: I2C Interrupt Status Register (Icstr)

    Overrun is detected. SPRUEN0D – March 2011 Submit Documentation Feedback Figure 15 and described in Reserved RSFULL R/W1C-0 ICXRDY ICRRDY R/W1C-1 R/W1C-0 3.9). © 2011, Texas Instruments Incorporated Registers Table XSMT ARDY NACK R/W1C-0 R/W1C-0 R/W1C-0 Inter-Integrated Circuit (I2C) Peripheral...
  • Page 26 0). • In the repeat mode (RM = 1): ARDY is set at the end of each data word transmitted from ICDXR. Inter-Integrated Circuit (I2C) Peripheral © 2011, Texas Instruments Incorporated www.ti.com SPRUEN0D – March 2011...
  • Page 27 • The I2C attempts to start a transfer while the BB (bus busy) bit is set to 1. When AL is set to 1, the MST and STP bits of ICMDR are cleared, and the I2C becomes a slave-receiver. SPRUEN0D – March 2011 Submit Documentation Feedback Inter-Integrated Circuit (I2C) Peripheral © 2011, Texas Instruments Incorporated Registers...

  • Page 28: I2C Clock Divider Registers (Icclkl And Icclkh)

    (ICCH + d) to produce the high-time duration of the I2C serial on the SCL pin. Inter-Integrated Circuit (I2C) Peripheral Section Figure 16 Reserved ICCL R/W-0 Figure 17 Reserved ICCH R/W-0 © 2011, Texas Instruments Incorporated www.ti.com 2.2. and described in Table and described in Table SPRUEN0D – March 2011 Submit Documentation Feedback...

  • Page 29: I2C Data Count Register (Iccnt)

    The start value loaded to internal data counter is 1-65535. SPRUEN0D – March 2011 Submit Documentation Feedback Figure 18 and described in Figure 18. I2C Data Count Register (ICCNT) Reserved ICDC R/W-0 © 2011, Texas Instruments Incorporated Registers Table Inter-Integrated Circuit (I2C) Peripheral...

  • Page 30: I2C Data Receive Register (Icdrr)

    I2C transmits when it is in the master-transmitter mode. Inter-Integrated Circuit (I2C) Peripheral Figure 19 and described in Figure 19. I2C Data Receive Register (ICDRR) Reserved Reserved © 2011, Texas Instruments Incorporated www.ti.com Table SADDR R/W-3FFh SPRUEN0D – March 2011 Submit Documentation Feedback...

  • Page 31: I2C Data Transmit Register (Icdxr)

    These reserved bit locations are always read as zeros. A value written to this field has no effect. 0-FFh Transmit data. SPRUEN0D – March 2011 Submit Documentation Feedback Figure 21 and described in Reserved Inter-Integrated Circuit (I2C) Peripheral © 2011, Texas Instruments Incorporated Registers Table R/W-0...

  • Page 32: I2C Mode Register (Icmdr)

    Figure 22. I2C Mode Register (ICMDR) Reserved Reserved R/W-0 R/W-0 R/W-0 Table Table © 2011, Texas Instruments Incorporated www.ti.com Table R/W-0 R/W-0 R/W-0 R/W-0 15). Note that the STT and STP bits can 15). Note that the STT and STP bits can SPRUEN0D –...
  • Page 33 Table 16 summarizes when TRX is used and when it is a don't care. Table Table Inter-Integrated Circuit (I2C) Peripheral © 2011, Texas Instruments Incorporated Registers Table 15). If the I2C is configured in slave mode, Figure 23. Note that...

  • Page 34: Master-Transmitter/Receiver Bus Activity Defined By Rm, Stt, And Stp Bits

    START condition, slave address, n data words (n = value in ICCNT) No activity STOP condition Repeat mode transfer: START condition, slave address, continuous data transfers until STOP condition or next START condition Reserved bit combination (No activity) © 2011, Texas Instruments Incorporated www.ti.com SPRUEN0D – March 2011 Submit Documentation Feedback...

  • Page 35: Block Diagram Showing The Effects Of The Digital Loopback Mode (Dlb) Bit

    TRX identifies the role of the I2C: TRX = 0: The I2C is a receiver. TRX = 1: The I2C is a transmitter. I2C peripheral ICDRR ICRSR ICSAR ICOAR ICXSR ICDXR Address/data Inter-Integrated Circuit (I2C) Peripheral © 2011, Texas Instruments Incorporated Registers...

  • Page 36: I2C Interrupt Vector Register (Icivr)

    Stop condition detected interrupt (SCD) Address-as-slave interrupt (AAS). Lowest priority if multiple I2C interrupts are pending. Inter-Integrated Circuit (I2C) Peripheral Figure 24 and described in Reserved Reserved © 2011, Texas Instruments Incorporated www.ti.com Table INTCODE SPRUEN0D – March 2011 Submit Documentation Feedback...

  • Page 37: I2C Extended Mode Register (Icemdr)

    The transmit data ready interrupt is generated when the data in ICDXR is copied to ICXSR. SPRUEN0D – March 2011 Submit Documentation Feedback Figure 25 and described in Reserved Reserved Inter-Integrated Circuit (I2C) Peripheral © 2011, Texas Instruments Incorporated Registers Table IGNACK R/W-0 R/W-1...

  • Page 38: I2C Prescaler Register (Icpsc)

    Note: IPSC must be initialized while the I2C is in reset (IRS = 0 in ICMDR). Inter-Integrated Circuit (I2C) Peripheral Figure 26 and described in Figure 26. I2C Prescaler Register (ICPSC) Reserved © 2011, Texas Instruments Incorporated www.ti.com Table IPSC R/W-0 SPRUEN0D – March 2011...

  • Page 39: I2C Peripheral Identification Register (Icpid1)

    TYPE Identifies type of peripheral. SPRUEN0D – March 2011 Submit Documentation Feedback Figure 27 Reserved Figure 28 Reserved Inter-Integrated Circuit (I2C) Peripheral © 2011, Texas Instruments Incorporated Registers and described in Table Revision R-6h and described in Table TYPE R-5h...

  • Page 40: Appendix A Revision History

    Changed Description of RM bit. Table 17 Changed Description of INTCODE bit, value = 1h. Changed Description of INTCODE bit, value = 7h. Revision History Table 22. Document Revision History © 2011, Texas Instruments Incorporated www.ti.com SPRUEN0D – March 2011 Submit Documentation Feedback...

  • Page 41: Important Notice

    Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

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