Sdram Control Pins - Texas Instruments TMS320C6201 Reference Manual

Table 9–10. SDRAM Control Pins
SDRAM
EMIF Signal Signal
SDA10 A10
SDRAS RAS
SDCAS CAS
SDWE WE
BE[3:0] DQM[3:0]
CE3, CE2 CS
or CE0
— CKE
CLKOUT2 CLK
SDCLK CLK
SDRAM Function
Address line A10/autoprecharge disable. Serves as a row address bit during
ACTV commands and also disables the autoprecharging function of SDRAM.
('C6201/C6202/C6701 only)
Row address strobe and command input. Latched by the rising edge of CLK to
determine current operation. Valid only if CS is active (low) during that clock
edge.
Column address strobe and command Input. Latched by the rising edge of CLK
to determine current operation. Valid only if CS is active (low) during that clock
edge.
Write strobe and command input. Latched by the rising edge of CLK to determine
current operation. Valid only if CS is active during that clock edge.
Data/output mask. DQM is an input/output buffer control signal. When high,
disables writes and places outputs in the high impedance state during reads.
DQM has a 2-CLK-cycle latency on reads and a 0-CLK-cycle latency on writes.
DQM pins serve essentially as byte strobes and are connected to BE[3:0]
outputs.
Chip select and command enable. CS must be active (low) for a command to be
clocked into the SDRAM. CS does not affect data input or output once a write
or read has begun. CE1 does not support SDRAM.
CKE clock enable. Tied high when interfaced to EMIF to enable clocking always.
SDRAM clock input. Runs at 1/2 the CPU clock rate.Used for synchronous
memory interface on the 'C6202.
SDRAM clock input. Runs at 1/2 the CPU clock rate.Used for SDRAM interface
on 'C6201/C6701
The SDRAM interface on the 'C6202 is identical to that of the 'C6201, with the
exception that it has been combined with the SBSRAM interface. Only one of
these two synchronous memory types can be used on a 'C6202 system. Since
the 'C6202 performs background refreshes for SDRAM, SBSRAM accesses
could be corrupted during SDRAM refresh if both memory types were present.
The SDRAM interface signals on the 'C6211/C6711 are identical to those of
the 'C6201, with the exception that EA12 performs the function of the SDA10
pin. The SDRAM signals have been combined with the SBSRAM and asyn-
chronous memory interface. An external clock source must be provided to the
'C6211/C6711, which generates the ECLKOUT signal used in the SDRAM in-
terface. The 'C6211/C6711 also allows for 8-, 16-, and 32-bit SDRAM inter-
SDRAM Interface
External Memory Interface 9-23