Peripheral Bus - Texas Instruments TMS320C6201 Reference Manual

2.7 Peripheral Bus

2.7.1 Byte and Halfword Access
Table 2–8. Memory Contents After Little-Endian or Big-Endian Data Stores
The peripherals are controlled by the CPU and the DMA controller through ac-
cesses of control registers. The CPU and the DMA controller access these reg-
isters through the peripheral data bus. The DMA controller directly accesses
the peripheral bus controller, whereas the CPU accesses it through the data
memory controller.
The peripheral bus controller converts all peripheral bus accesses to word
accesses. However, on read accesses both the CPU and the DMA controller
can extract the correct portions of the word to perform byte and halfword ac-
cesses properly. Any side-effects caused by a peripheral control register read
occur regardless of which bytes are read. In contrast, for byte or halfword
writes, the values the CPU and the DMA controller only provide correct values
in the enabled bytes. The values that are always correct are shown in
Table 2–8. Undefined results are written to the nonenabled bytes. If you are
not concerned about the values in the disabled bytes, this is acceptable. Other-
wise, access the peripheral registers only via word accesses.
Access Address Bits
Type (1:0)
Word
Halfword
Halfword
Byte
Byte
Byte
Byte
Note: X indicates nybbles correctly written, ? indicates nybbles with undefined value after
write
TMS320C6201/C6701 Program and Data Memory
Big-Endian
Register
00 XXXXXXXX
00 XXXX????
10 ????XXXX
00 XX??????
01 ??XX????
10 ????XX??
11 ??????XX
Peripheral Bus
Little-Endian
Memory Result
XXXXXXXX
????XXXX
XXXX????
??????XX
????XX??
??XX????
XX??????
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