Page 1 C28x DSP Design Workshop Student Guide C28x Revision 5.0 February 2004 Technical Training Organization...
Page 2: Important Notice
Important Notice Important Notice Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete.
Page 3 Technical Training Technical Training eZdsp is a trademark of Spectrum Digital, Inc. eZdsp is a trademark of Spectrum Digital, Inc. Copyright © 2004 Texas Instruments. All rights reserved. Copyright © 2004 Texas Instruments. All rights reserved. Organization Organization Introductions Introductions...
Page 4: Architecture Overview
C28x Workshop C28x Workshop Outline C28x Workshop Outline C28x Workshop Outline Architecture Overview Architecture Overview Programming Development Environment Programming Development Environment Peripheral Register Header Files Peripheral Register Header Files Reset and Interrupts Reset and Interrupts System Initialization System Initialization Analog Digital Converter Analog Digital Converter...
Page 5 This architecture overview introduces the basic architecture of the TMS320C28x (C28x) series of Digital Signal Processors from Texas Instruments. The C28x series adds a new level of general purpose processing ability unseen in any previous DSP chips. The C28x is ideal for applications combining DSP, standard microcontroller processing, efficient C code execution, or operating system tasks.
Page 6: Table Of Contents
Module Topics Module Topics Architecture Overview..........................1-1 Module Topics............................1-2 What is the TMS320C28x?........................1-3 C28x CPU ............................... 1-4 Multiplier, ALU, and Shifters......................1-5 TMS320C28x Internal Bussing ......................1-6 Special Instructions..........................1-7 Pipeline Advantage..........................1-8 Memory ..............................1-9 Memory Map ............................1-9 Code Security Module (CSM) ......................1-10 Peripherals ............................1-10 Fast Interrupt Response .........................1-11...
Page 7: What Is The Tms320C28X
What is the TMS320C28x? What is the TMS320C28x? The TMS320C28x is a 32-bit fixed point DSP that specializes in high performance control applications such as, robotics, industrial automation, mass storage devices, lighting, optical networking, power supplies, and other control applications needing a single processor to solve a high performance application.
Page 8: C28X Cpu
C28x CPU C28x CPU The C28x is a highly integrated, high performance solution for demanding control applications. The C28x is a cross between a general microcontroller and a digital signal processor, balancing the code density of a RISC chip and the execution speed of a DSP with the architecture, firmware, and development tools of a microcontroller.
Page 9: Multiplier, Alu, And Shifters
C28x CPU Multiplier, ALU, and Shifters C28x Multiplier and ALU / Shifters C28x Multiplier and ALU / Shifters Program Bus Program Bus Data Bus Data Bus 16/32 16/32 XT (32) or T/TL XT (32) or T/TL MULTIPLIER MULTIPLIER 32 x 32 or 32 x 32 or 8/16 8/16...
Page 10: Tms320C28X Internal Bussing
C28x CPU TMS320C28x Internal Bussing As with many DSP type devices, multiple busses are used to move data between the memories and peripherals and the CPU. The C28x memory bus architecture contains: • A program read bus (22 bit address line and 32 bit data line) •...
Page 11: Special Instructions
C28x CPU Special Instructions C28x Atomic Read/Modify/Write C28x Atomic Read/Modify/Write Atomic Instructions Benefits: Atomic Instructions Benefits: Simpler programming Simpler programming LOAD LOAD READ READ Smaller, faster code Smaller, faster code Registers Registers ALU / MPY ALU / MPY Uninterruptible (Atomic) Uninterruptible (Atomic) WRITE WRITE...
Page 12: Pipeline Advantage
C28x CPU Pipeline Advantage C28x Pipeline C28x Pipeline stage pipeline stage pipeline E & G Access E & G Access same address same address F1: Instruction Address F1: Instruction Address Protected Pipeline Protected Pipeline F2: Instruction Content F2: Instruction Content D1: Decode Instruction D1: Decode Instruction Order of results are as written in...
Page 13: Memory
Memory Memory The memory space on the C28x is divided into program and data space. There are several different types of memory available that can be used as both program or data space. They include the flash memory, single access RAM (SARAM), expanded SARAM, and Boot ROM which is factory programmed with boot software routines or standard tables used in math related algorithms.
Page 14: Code Security Module (Csm)
Memory Code Security Module (CSM) Code Security Module Code Security Module Prevents reverse engineering and Prevents reverse engineering and protects valuable intellectual property protects valuable intellectual property 0x00 8000 0x00 8000 LO SARAM (4K) LO SARAM (4K) 0x00 9000 0x00 9000 L1 SARAM (4K) L1 SARAM (4K) 0x00 A000...
Page 15: Fast Interrupt Response
Fast Interrupt Response Fast Interrupt Response The fast interrupt response, with automatic context save of critical registers, resulting in a device that is capable of servicing many asynchronous events with minimal latency. C28x implements a zero cycle penalty to do 14 registers context saved and restored during an interrupt. This feature helps reduces the interrupt service routine overheads.
Page 16: C28 Mode
C28 Mode C28 Mode The C28x is one of several members of the fixed-point generations of digital signal processors (DSPs) in the TMS320 family. The C28x is source-code and object-code compatible with the C27x. In addition, the C28x is source code compatable with the 24x/240x DSP and previously written code can be reassembled to run on a C28x device.
Page 17: Reset
Reset Reset Reset – Bootloader Reset – Bootloader Reset Reset OBJMODE=0 AMODE=0 OBJMODE=0 AMODE=0 ENPIE=0 VMAP=1 ENPIE=0 VMAP=1 Bootloader sets Bootloader sets XMPNMC=0 XMPNMC=0 OBJMODE = 1 OBJMODE = 1 (microcomputer mode) (microcomputer mode) AMODE = 0 AMODE = 0 Reset vector fetched Reset vector fetched Boot determined by...
Page 18: Summary
Summary Summary Summary Summary High performance 32 bit DSP High performance 32 bit DSP 32 x 32 bit or dual 16 x 16 bit MAC 32 x 32 bit or dual 16 x 16 bit MAC Atomic read modify write instructions Atomic read modify write instructions...
Page 19 Programming Development Environment Introduction This module will explain how to use Code Composer Studio (CCS) integrated development environment (IDE) tools to develop a program. Creating projects and setting building options will be covered. Use and the purpose of the linker command file will be described. Additionally, the DSP/BIOS Configuration Tool will be used to handle system memory and system setup.
Page 20: Module Topics
Module Topics Module Topics Programming Development Environment ....................2-1 Module Topics............................2-2 Code Composer Studio ........................... 2-3 Software Development and COFF Concepts..................2-3 Projects ............................... 2-5 Build Options............................2-6 Creating a Linker Command File ......................2-9 Sections .............................. 2-9 Linker Command Files (.cmd) ......................2-12 Memory-Map Description .........................2-12 Section Placement..........................2-14 Exercise 2a.............................2-15...
Page 21: Code Composer Studio
Code Composer Studio Code Composer Studio Software Development and COFF Concepts In an effort to standardize the software development process, TI uses the Common Object File Format (COFF). COFF has several features which make it a powerful software development system. It is most useful when the development task is split between several programmers. Each file of code, called a module, may be written independently, including the specification of all resources necessary for the proper operation of the module.
Page 22 Code Composer Studio The concept of COFF tools is to allow modular development of software independent of hardware concerns. An individual assembly language file is written to perform a single task and may be linked with several other tasks to achieve a more complex total system. Writing code in modular form permits code to be developed by several people working in parallel so the development cycle is shortened.
Page 23: Projects
Code Composer Studio Projects Code Composer works with a project paradigm. Essentially, within CCS you create a project for each executable program you wish to create. Projects store all the information required to build the executable. For example, it lists things like: the source files, the header files, the target system’s memory-map, and program build options.
Page 24: Build Options
Code Composer Studio Build Options Project options direct the code generation tools (i.e. compiler, assembler, linker) to create code according to your system’s needs. When you create a new project, CCS creates two sets of build options – called Configurations: one called Debug, the other Release (you might think of as Optimize).
Page 25 Code Composer Studio Build Options GUI Linker Build Options GUI Linker GUI has 2 categories GUI has 2 categories for linking for linking Specifies various link Specifies various link options options “. Debug ” indicates “. Debug ” indicates on subfolder level on subfolder level below project (.
Page 26 Code Composer Studio Default Build Configurations Default Build Configurations For new projects, CCS automatically For new projects, CCS automatically creates two build configurations: creates two build configurations: Debug Debug unoptimized unoptimized Release (optimized) Release (optimized) Use the drop down menu to quickly Use the drop down menu to quickly select the build configuration...
Page 27: Creating A Linker Command File
Creating a Linker Command File Creating a Linker Command File Sections Looking at a C program, you'll notice it contains both code and different kinds of data (global, local, etc.). Sections Sections Global Vars (. ebss) Init vals ( cinit) ebss cinit Every C program...
Page 28 Creating a Linker Command File Following is a list of the sections that are created by the compiler. Along with their description, we provide the Section Name defined by the compiler. Compiler Section Names Compiler Section Names Initialized Sections Initialized Sections Name Description Link Location...
Page 29 Creating a Linker Command File Placing Sections in Memory Placing Sections in Memory Memory Memory Sections Sections 0x00 0000 0x00 0000 M0SARAM M0SARAM (0x400) (0x400) ebss ebss 0x00 0400 0x00 0400 M1SARAM M1SARAM (0x400) (0x400) .stack .stack cinit cinit 0x3D 8000 0x3D 8000 FLASH FLASH...
Page 30: Linker Command Files (.Cmd)
Creating a Linker Command File Linker Command Files (.cmd) The linker concatenates each section from all input files, allocating memory to each section based on its length and location as specified by the MEMORY and SECTIONS commands in the linker command file.
Page 31 Creating a Linker Command File Remember that the DSP has two memory maps: Program, and Data. Therefore, the MEMORY description must describe each of these separately. The loader uses the following syntax to delineate each of these: Linker Page TI Definition Page 0 Program Page 1...
Page 32: Section Placement
Creating a Linker Command File Section Placement You can specify how you want the sections to be distributed through memory. You would use the following code to link the sections into the memory specified in the previous example: SECTIONS .text:> FLASH PAGE 0 .ebss:>...
Page 33: Exercise 2A
Exercise 2a Exercise 2a Looking at the following block diagram, and create a linker command file. Exercise 2a Exercise 2a 0x00 0000 0x00 0000 0x00 0400 0x00 0400 M0SARAM M0SARAM M1SARAM M1SARAM (0x400) (0x400) (0x400) (0x400) 0x00 8000 0x00 8000 0x00 9000 0x00 9000 L0SARAM...
Page 34: Summary: Linker Command File
Exercise 2a Summary: Linker Command File The linker command file (.cmd) contains the inputs — commands — for the linker. This information is summarized below: Linker Command File Summary Linker Command File Summary Memory Map Description Memory Map Description Name Name Location Location...
Page 35: Lab 2A: Linker Command File
Lab 2a: Linker Command File Lab 2a: Linker Command File Objective Create a linker command file and link the C program file (LAB2.C) into the system described below. Lab 2a: Linker Command File Lab 2a: Linker Command File 0x00 0000 0x00 8000 0x00 0000 0x00 8000...
Page 36 Lab 2a: Linker Command File The window on the left is the project window and the large right hand window is your workspace. 2. A project is all the files you will need to develop an executable output file (.out) which can be run on the DSP hardware.
Page 37 Lab 2a: Linker Command File 12. In the Sections{} area, notice that a section called .reset has already been allocated. The .reset section is part of the rts2800_ml.lib, and is not needed. By putting the TYPE = DSECT modifier after its allocation, the linker will ignor this section and not allocate it. 13.
Page 38 Lab 2a: Linker Command File Type “&z” into the address field. Note that you must use the ampersand (meaning "address of") when using a symbol in a memory window address box. Also note that Code Composer Studio is case sensitive. Set the properties format to “Hex –...
Page 39: Dsp/Bios Configuration Tool
DSP/BIOS Configuration Tool DSP/BIOS Configuration Tool The DSP/BIOS Configuration Tool (often called Config Tool or GUI Tool or GUI) creates and modifies a system file called the Configuration DataBase (.CDB). If we talk about using CDB files, we’re also talking about using the Config Tool. DSP/BIOS Configuration Tool DSP/BIOS Configuration Tool (file .
Page 40 DSP/BIOS Configuration Tool 1. Creating a New Memory Region (Using MEM) First, to create a specific memory area, open up the .CDB file, right-click on the Memory Section Manager and select “Insert MEM”. Give this area a unique name and then specify its base and length.
Page 41 DSP/BIOS Configuration Tool 2. Placing Sections – MEM Manager Properties The configuration tool makes it easy to place sections. The predefined compiler sections that were described earlier each have their own drop-down menu to select one of the memory regions you defined (in step 1).
Page 42 DSP/BIOS Configuration Tool 3. Running the Linker Creating the Linker Command File (via .CDB) When you have finished creating memory regions and allocating sections into these memory areas (i.e. when you save the .CDB file), the CCS configuration tool creates five files. One of the files is BIOS’s cfg.cmd file —...
Page 43 DSP/BIOS Configuration Tool Running the Linker The linker’s main purpose is to link together various object files. It combines like-named input sections from the various object files and places each new output section at specific locations in memory. In the process, it resolves (provides actual addresses for) all of the symbols described in your code.
Page 44: Lab 2B: Dsp/Bios Configuration Tool
Lab 2b: DSP/BIOS Configuration Tool Lab 2b: DSP/BIOS Configuration Tool Objective Use Code Composer Studio and DSP/BIOS configuration tool to create a configuration database files (*.CDB). The generated linker command file Labcfg.cmd will be then be used with Lab2.c to verify its operation. The memory and sections of a “user” linker command file will be deleted, however, the “user”...
Page 45 Lab 2b: DSP/BIOS Configuration Tool Lab2.pjt from the Project Recent Project Files list. This will put you at the proper starting point for this lab exercise. 2. If needed, verify that the project is open in CCS by left clicking the plus sign (+) to the left of Project.
Page 46 Lab 2b: DSP/BIOS Configuration Tool combined M0SARAM and M1SARAM into a single memory block called M0SARAM. We want to split these memory sections as shown in the slide for this lab exercise. Right click on MEM – Memory Section Manager and select Insert MEM. Rename the newly added memory section to L1SARAM.
Page 47 Lab 2b: DSP/BIOS Configuration Tool 19. Next, single-step the routine through to the end. Check to see if the program is working as expected. You should get the same value for “z” as in Lab2a. End of Exercise C28x - Programming Development Environment 2 - 29...
Page 48: Solutions
Solutions Solutions Exercise 2a Solution Exercise 2a Solution Memory Memory PAGE PAGE /* Program Space */ /* Program Space */ FLASH org = 0x3D8000 0x20000 FLASH org = 0x3D8000 0x20000 PAGE 1 /* Data Space */ PAGE 1 /* Data Space */ M0SARAM M0SARAM org =...
Page 49 Peripherial Registers Header Files Introduction The purpose of the F281x C-code header files is to simplify the programming of the many peripherals on the C28x device. Typically, to program a peripheral the programmer needs to write the appropriate values to the different fields within a control register. In it’s simplest form, the process consists of writing a hex value (or masking a bit field) to the correct address in memory.
Page 50: Module Topics
Module Topics Module Topics Peripherial Registers Header Files ......................3-1 Module Topics............................3-2 Traditional and Structure Approach to C Coding .................. 3-3 Naming Conventions..........................3-6 Example of Peripheral Structure .h file ....................3-7 Mapping Structures to Memory ......................3-8 Linker Command File......................... 3-8 F281x C-Code Header Files ........................
Page 51: Traditional And Structure Approach To C Coding
Traditional and Structure Approach to C Coding Traditional and Structure Approach to C Coding Traditional Approach to C Coding Traditional Approach to C Coding #define ADCTRL1 #define ADCTRL1 (volatile unsigned (volatile unsigned *)0x00007100 *)0x00007100 #define ADCTRL2 #define ADCTRL2 (volatile unsigned (volatile unsigned *)0x00007101 *)0x00007101...
Page 52 Traditional and Structure Approach to C Coding The CCS Watch Window using Structures The CCS Watch Window using Structures The CCS Watch Window using #define The CCS Watch Window using #define 3 - 4 C28x - Peripheral Registers Header Files...
Page 53 Traditional and Structure Approach to C Coding Is the Structure Approach Efficient? Is the Structure Approach Efficient? The structure approach enables efficient compiler use of The structure approach enables efficient compiler use of DP addressing mode and C28x Atomic operations DP addressing mode and C28x Atomic operations C Source Code Generated Assembly Code...
Page 54: Naming Conventions
Naming Conventions Naming Conventions The header files use a familiar set of naming conventions. They are consistent with the Code Composer Studio configuration tool, and generated file naming conventions Structure Naming Conventions Structure Naming Conventions The DSP281x header files define: The DSP281x header files define: All of the peripheral structures All of the peripheral structures...
Page 55: Example Of Peripheral Structure .H File
Example of Peripheral Structure .h file Example of Peripheral Structure .h file Example of Peripheral Structure .h file Example of Peripheral Structure .h file Example Example Adc.h /* ADC Individual Register Bit Definitions */ /* ADC Individual Register Bit Definitions */ struct struct ADCTRL1_BITS {...
Page 56: Mapping Structures To Memory
Mapping Structures to Memory Mapping Structures to Memory The data structures describe the register set in detail. And, each instance of the data type (i.e., register set) is unique. Each structure is associated with an address in memory. This is done by (1) creating a new section name via a DATA_SECTION pragma, and (2) linking the new section name to a specific memory in the linker command file.
Page 57: F281X C-Code Header Files
F281x C-Code Header Files F281x C-Code Header Files The C-code header files consists of .h, c source files, linker command files, and other useful example programs, documentations and add-ins for Code Composer Studio. DSP281x Header File Package DSP281x Header File Package (http://www.
Page 58: Definition Files
F281x C-Code Header Files .h Definition Files The DSP281x_Device.h header file is the main include file. By including this file in the .c source code, all of the peripheral specific .h header files are automatically included. Of course, each specific .h header file can included individually in an application that do not use all the header files, or you can comment out the ones you do not need.
Page 59: Global Variable Definition File
F281x C-Code Header Files Global Variable Definition File With DSP281x_GlobalVariableDefs.c included in the project all the needed variable definitions are globally defined. Global Variable Definition File Global Variable Definition File DSP281x_ GlobalVariableDefs DSP281x_ GlobalVariableDefs Defines all variables to use .h files Defines all variables to use .h files DATA_SECTION pragma...
Page 60: Peripheral Specific Routines
Peripheral Specific Routines Peripheral Specific Routines Peripheral Specific C functions are used to initialize the peripherals. They are used by adding the appropriate .c file to the project. Peripheral Specific Routines Peripheral Specific Routines Contains peripheral specific Contains peripheral specific initialization routines and other initialization routines and other support functions...
Page 61: Example Usage Flow
Example Usage Flow Example Usage Flow // Step 0. Include required header files // DSP281x_Device.h: device specific definitions #include statements // for all of the peripheral .h definition files. // DSP281x_Example.h is specific for the given example. #include "DSP281x_Device.h" // Prototype statements for functions found within this file. interrupt void cpu_timer0_isr(void);...
Page 62 Example Usage Flow EALLOW; // This is needed to write to EALLOW protected registers PieVectTable.TINT0 = &cpu_timer0_isr; EDIS; // This is needed to disable write to EALLOW protected registers // Include application specific functions. This is for this example: // Configure CPU-Timer 0 to interrupt every second: ConfigCpuTimer(&CpuTimer0, 100, 1000000);...
Page 63: Summary
Summary Summary Peripheral Register Header Files Peripheral Register Header Files Summary Summary Easier code development Easier code development Easy to use Easy to use Generates most efficient Code Generates most efficient Code Increases Effectiveness of CCS Increases Effectiveness of CCS Watch Window Watch Window TI has already done all the work!
Page 64 Summary 3 - 16 C28x - Peripheral Registers Header Files...
Page 65 Reset and Interrupts Introduction This module describes the interrupt process and explains how the peripheral Interrupt expansion (PIE) works. Learning Objectives Learning Objectives Learning Objectives Describe the C28x reset process Describe the C28x reset process and post reset device state and post reset device state List the event sequence during an...
Page 66: Module Topics
Module Topics Module Topics Reset and Interrupts ..........................4-1 Module Topics............................4-2 Core Interrupt Lines ..........................4-3 Reset ..............................4-3 Reset - Bootloader ..........................4-5 Interrupt Sources ............................ 4-7 Interrupt Processing..........................4-7 Peripheral Interrupt Expansion (PIE) ....................4-9 PIE Interrupt Vector Table ........................4-10 Interrupt Response and Latency ......................4-13 4 - 2 C28x - Reset and Interrupts...
Page 67: Core Interrupt Lines
Core Interrupt Lines Core Interrupt Lines C28x Core Interrupt Lines C28x Core Interrupt Lines INT1 INT1 INT2 INT2 2 non maskable 2 non maskable INT3 INT3 interrupts (RS, interrupts (RS, INT4 INT4 “selectable” NMI) “selectable” NMI) INT5 INT5 C28x C28x INT6 INT6 maskable...
Page 68 Core Interrupt Lines Register Bits Initialized at Reset Register Bits Initialized at Reset Register bits defined by reset Register bits defined by reset 0x3F FFC0 PC loaded with reset vector 0x3F FFC0 PC loaded with reset vector 0x0000 0000 Accumulator cleared 0x0000 0000 Accumulator cleared XAR0...
Page 69: Reset - Bootloader
Core Interrupt Lines Reset - Bootloader Reset – Bootloader Reset – Bootloader XMPNMC=1 XMPNMC=1 (microprocessor mode) (microprocessor mode) Reset Reset Reset vector fetched Reset vector fetched from XINTF zone 7 from XINTF zone 7 OBJMODE=0 AMODE=0 OBJMODE=0 AMODE=0 0x3F FFC0 0x3F FFC0 ENPIE=0 VMAP=1...
Page 70 Core Interrupt Lines Reset Code Flow Summary Reset Code Flow Summary 0x3D 7800 0x3D 7800 OTP (1K) OTP (1K) 0x3D 8000 0x3D 8000 FLASH (128K) FLASH (128K) 0x3F 7FF6 0x3F 7FF6 0x3F 8000 0x3F 8000 H0 SARAM (8K) H0 SARAM (8K) Execution Entry Execution Entry 0x3F F000...
Page 71: Interrupt Sources
Interrupt Sources Interrupt Sources Interrupt Sources Interrupt Sources Internal Sources Internal Sources TINT2 TINT2 C28x CORE C28x CORE TINT1 TINT1 TINT0 TINT0 EV and Non EV and Non INT1 INT1 Peripherals Peripherals (Peripheral (Peripheral (EV, ADC, SPI, INT2 (EV, ADC, SPI, INT2 Interrupt Interrupt...
Page 72 Interrupt Sources Interrupt Flag Register (IFR) Interrupt Flag Register (IFR) RTOSINT RTOSINT DLOGINT DLOGINT INT14 INT14 INT13 INT13 INT12 INT12 INT11 INT11 INT10 INT10 INT9 INT9 INT8 INT8 INT7 INT7 INT6 INT6 INT5 INT5 INT4 INT4 INT3 INT3 INT2 INT2 INT1 INT1 Pending :...
Page 73: Peripheral Interrupt Expansion (Pie)
Interrupt Sources Interrupt Global Mask Bit Interrupt Global Mask Bit Bit 0 Bit 0 INTM INTM INTM used to globally enable/disable interrupts: INTM used to globally enable/disable interrupts: Enable: INTM = 0 Enable: INTM = 0 Disable: INTM = 1 (reset value) Disable: INTM = 1 (reset value) INTM modified from assembly code only:...
Page 74: Pie Interrupt Vector Table
Interrupt Sources PIE Registers PIE Registers PIEIFRx register (x = 1 to 12) PIEIFRx register (x = 1 to 12) reserved INTx.8 INTx INTx INTx.7 INTx.6 INTx INTx INTx.5 INTx.4 INTx INTx INTx.3 INTx.2 INTx INTx INTx.1 PIEIERx register (x = 1 to 12) PIEIERx register (x = 1 to 12)
Page 75 Interrupt Sources PIE Vector Mapping (ENPIE = 1) PIE Vector Mapping (ENPIE = 1) Vector name Vector name PIE vector address PIE vector address PIE vector Description PIE vector Description Not used Not used 0x00 0D00 0x00 0D00 Reset Vector Never Fetched Here Reset Vector Never Fetched Here INT1 INT1...
Page 76 Interrupt Sources Device Vector Mapping Summary Device Vector Mapping Summary RESET RESET MPNMC = 1 (external memory XINTF) MPNMC = 1 (external memory XINTF) MPNMC = 0 (on- chip ROM memory) MPNMC = 0 (on chip ROM memory) Reset Vector <0x3F FFCO> = _c_int00 Reset Vector <0x3F FFCO>...
Page 77: Interrupt Response And Latency
Interrupt Sources Interrupt Response and Latency Interrupt Response Hardware Sequence Interrupt Response Hardware Sequence CPU Action Description CPU Action Description → → Registers Registers stack stack 14 Register words auto saved 14 Register words auto saved → → IFR (bit) Clear corresponding IFR bit IFR (bit) Clear corresponding IFR bit...
Page 78 Interrupt Sources 4 - 14 C28x - Reset and Interrupts...
Page 79: System Initialization
System Initialization Introduction This module discusses the operation of the OSC/PLL-based clock module and watchdog timer. Also, various low power modes, general-purpose digital I/O ports, and the EALLOW protected registers will be covered. Learning Objectives Learning Objectives Learning Objectives OSC/PLL Clock Module OSC/PLL Clock Module Watchdog Timer Watchdog Timer...
Page 80: Module Topics
Module Topics Module Topics System Initialization..........................5-1 Module Topics............................5-2 Oscillator/PLL Clock Module......................... 5-3 Watchdog Timer............................5-5 Low Power Modes........................... 5-9 General-Purpose Digital I/O .........................5-11 EALLOW Protected Registers........................5-14 Lab 5: System Initialization ........................5-15 5 - 2 C28x - System Initialization...
Page 81: Oscillator/Pll Clock Module
Oscillator/PLL Clock Module Oscillator/PLL Clock Module C28x Oscillator / PLL Clock Module C28x Oscillator / PLL Clock Module PLLCR @ 0x007021 PLLCR @ 0x007021 (lab file: (lab file: SysCtrl SysCtrl Watchdog Watchdog X1 /CLKIN X1 /CLKIN CLKIN CLKIN Module C28x Module C28x Core...
Page 82 Oscillator/PLL Clock Module Peripheral Clock Control Register Peripheral Clock Control Register PCLKCR @ 0x00701C PCLKCR @ 0x00701C (lab file: SysCtrl (lab file: SysCtrl LSPCLK LSPCLK eCANA SCIB SCIA SPIA reserved reserved reserved ENCLK ENCLK ENCLK ENCLK ENCLK HSPCLK HSPCLK reserved reserved reserved reserved...
Page 83: Watchdog Timer
Watchdog Timer Watchdog Timer Watchdog Timer Watchdog Timer Resets the C28x if the CPU crashes Resets the C28x if the CPU crashes Watchdog counter runs independent of CPU Watchdog counter runs independent of CPU If counter overflows, reset or interrupt is If counter overflows, reset or interrupt is triggered triggered...
Page 84 Watchdog Timer Watchdog Timer Module Watchdog Timer Module (lab file: (lab file: SysCtrl SysCtrl SCSR . 0 SCSR . 0 OSCCLK OSCCLK WDOVERRIDE WDOVERRIDE WDPS WDPS Free Free WDCR . 2 • WDCR . 2 • /512 /512 Running Running •...
Page 85 Watchdog Timer Watchdog Timer Control Register Watchdog Timer Control Register WDCR @ 0x007029 WDCR @ 0x007029 (lab file: SysCtrl (lab file: SysCtrl WD Flag Bit WD Flag Bit Gets set when the WD causes a reset Gets set when the WD causes a reset •...
Page 86 Watchdog Timer WDKEY Write Results WDKEY Write Results Sequential Value Written Sequential Value Written Step Step to WDKEY to WDKEY Result Result No action No action No action No action WD counter enabled for reset on next AAh write WD counter enabled for reset on next AAh write WD counter enabled for reset on next AAh write WD counter enabled for reset on next AAh write WD counter enabled for reset on next AAh write...
Page 87: Low Power Modes
Low Power Modes Low Power Modes Low Power Modes Low Power Modes Low Power CPU Logic Watchdog PLL / Low Power CPU Logic Peripheral Watchdog PLL / Peripheral Mode Clock Clock Mode Clock Logic Clock Clock Logic Clock Normal Run Normal Run IDLE IDLE...
Page 88 Low Power Modes Low Power Mode Control Register 1 Low Power Mode Control Register 1 LPMCR1 @ 0x00701F LPMCR1 @ 0x00701F (lab file: SysCtrl (lab file: SysCtrl CANRXA CANRXA SCIRXB SCIRXB SCIRXA SCIRXA C6TRIP C6TRIP C5TRIP C5TRIP C4TRIP C4TRIP C3TRIP C3TRIP C2TRIP C2TRIP...
Page 89: General-Purpose Digital I/O
General-Purpose Digital I/O General-Purpose Digital I/O F2812 GPIO Pin Assignment F2812 GPIO Pin Assignment GPIO A GPIO A GPIO B GPIO B GPIO D GPIO D GPIOA0 / PWM1 GPIOA0 / PWM1 GPIOB0 / PWM7 GPIOB0 / PWM7 GPIOD0 / T1CTRIP_PDPINTA GPIOD0 / T1CTRIP_PDPINTA GPIOA1 / PWM2 GPIOB1 / PWM8...
Page 90 General-Purpose Digital I/O C28x GPIO Functional Block Diagram C28x GPIO Functional Block Diagram GPxSET GPxSET GPxCLEAR GPxCLEAR GPxTOGGLE GPxTOGGLE Primary Primary GPxDAT GPxDAT Peripheral Peripheral Function Function I/O DAT I/O DAT • • Bit (R/W) Bit (R/W) • • • •...
Page 91 General-Purpose Digital I/O C28x GPIO Data Registers C28x GPIO Data Registers (lab file: Gpio (lab file: Gpio Address Address Register Register Name Name 0x0070E0 0x0070E0 GPADAT GPADAT GPIO A Data Register GPIO A Data Register 0x0070E1 GPASET GPIO A Set Register 0x0070E1 GPASET GPIO A Set Register...
Page 92: Eallow Protected Registers
EALLOW Protected Registers EALLOW Protected Registers EALLOW Protected Registers EALLOW Protected Registers Register Name Address Range size (x16) Register Name Address Range size (x16) Device Emulation 0x00 0880 – 0x00 09FF Device Emulation 0x00 0880 – 0x00 09FF FLASH 0x00 0A00 –...
Page 93: Lab 5: System Initialization
Lab 5: System Initialization Lab 5: System Initialization Objective The objective of this lab is to perform the processor system initialization by applying the techniques discussed in module 5. Additionally, the peripheral interrupt expansion (PIE) vectors will be initialized and tested using the information discussed in the previous module. This initialization process will be used again in the module 6 analog-to-digital converter lab, and the module 7 event manager lab.
Page 94 Lab 5: System Initialization Project Build Options 2. We need to setup the search path to include the peripheral register header files. Click: Project Build Options… Select the Compiler tab. In the Preprocessor Category, find the Include Search Path (-i) box and enter: ..\DSP281x_headers\include This is the path for the header files.
Page 95 Lab 5: System Initialization Run the Code – Watchdog Reset 9. Place the cursor on the first line of code in main() and set a breakpoint by right clicking the mouse key and select Toggle breakpoint. Notice that line is highlighted with a red dot indicating that the breakpoint has been set.
Page 96 Lab 5: System Initialization 18. Modify main() to do the following: enable the "WAKEINT" interrupt in the PIE (Hint: use the PieCtrlRegs structure) enable core INT1 (IER register) enable global interrupts (INTM bit) 19. In SysCtrl.c modify the system control and status register (SCSR) to cause the watchdog to generate a WAKEINT rather than a reset.
Page 97 Analog-to-Digital Converter Introduction This module explains the operation of the analog-to-digital converter. The system consists of a 12-bit analog-to-digital converter with 16 analog input channels. The analog input channels have a range from 0 to 3 volts. Two input analog multiplexers are used, each supporting 8 analog input channels.
Page 98: Module Topics
Module Topics Module Topics Analog-to-Digital Converter........................6-1 Module Topics............................6-2 Analog-to-Digital Converter........................6-3 Analog-to-Digital Converter Registers....................6-5 Example – Sequencer “Start/Stop” Operation ...................6-10 ADC Conversion Result Buffer Register...................6-11 Numerical Format..........................6-12 Lab 6: Analog-to-Digital Converter ......................6-13 6 - 2 C28x - Analog-to-Digital Converter...
Page 99: Analog-To-Digital Converter
Analog-to-Digital Converter Analog-to-Digital Converter ADC Module Block Diagram ADC Module Block Diagram (Cascaded Mode) (Cascaded Mode) Analog MUX Analog MUX ADCINA0 ADCINA0 Result MUX Result MUX ADCINA1 ADCINA1 RESULT0 RESULT0 RESULT1 RESULT1 ADCINA7 ADCINA7 bit A/D bit A/D RESULT2 RESULT2 Converter Converter ADCINB0...
Page 100: Analog-To-Digital Converter
Analog-to-Digital Converter ADC Module ADC Module bit resolution ADC core bit resolution ADC core Sixteen analog inputs (range of 0 to 3V) Sixteen analog inputs (range of 0 to 3V) Two analog input multiplexers Two analog input multiplexers Up to 8 analog input channels each Up to 8 analog input channels each Two sample/hold units (for each input Two sample/hold units (for each input...
Page 101: Analog-To-Digital Converter Registers
Analog-to-Digital Converter Analog-to-Digital Converter Registers Analog Digital Converter Registers Analog Digital Converter Registers (lab file: (lab file: Register Address Description Register Address Description ADCTRL1 ADCTRL1 0x007100 0x007100 ADC Control Register 1 ADC Control Register 1 ADCTRL2 ADCTRL2 0x007101 0x007101 ADC Control Register 2 ADC Control Register 2 ADCMAXCONV 0x007102 ADCMAXCONV 0x007102...
Page 102 Analog-to-Digital Converter ADC Control Register 1 ADC Control Register 1 Upper Byte Upper Byte ADCTRL1 @ 0x007100 ADCTRL1 @ 0x007100 (lab file: (lab file: ADC Module Reset ADC Module Reset Acquisition Time Prescale (S/H) Acquisition Time Prescale (S/H) 0 = no effect 0 = no effect Value = (binary+1) Value = (binary+1)
Page 103 Analog-to-Digital Converter ADC Control Register 2 ADC Control Register 2 Upper Byte Upper Byte ADCTRL2 @ 0x007101 ADCTRL2 @ 0x007101 (lab file: (lab file: EVB SOC EVB SOC EVA SOC EVA SOC (cascaded mode only) (cascaded mode only) SEQ1 Mask Bit SEQ1 Mask Bit 0 = no action 0 = no action...
Page 104 Analog-to-Digital Converter ADC Control Register 3 ADC Control Register 3 ADCTRL3 @ 0x007118 ADCTRL3 @ 0x007118 (lab file: (lab file: ADC Reference Bandgap ADC Power Down ADC Reference Bandgap ADC Power Down Power Down Power Down (except Bandgap & Ref.) Power Down Power Down (except...
Page 105 Analog-to-Digital Converter ADC Input Channel Select Sequencing ADC Input Channel Select Sequencing Control Register Control Register (lab file: (lab file: Bits 15 Bits 15 Bits 11 Bits 11 Bits 7 Bits 7 Bits 3 Bits 3 CONV03 CONV02 CONV01 CONV00 CONV03 CONV02 CONV01 CONV00 ADCCHSELSEQ1 ADCCHSELSEQ1...
Page 106: Example - Sequencer "Start/Stop" Operation
Analog-to-Digital Converter Example – Sequencer “Start/Stop” Operation Example Sequencer “Start/Stop” Example Sequencer “Start/Stop” Operation Operation Timer 1 Timer 1 System Requirements: System Requirements: • Three autoconversions ) off trigger 1 (Timer underflow) • Three autoconversions ) off trigger 1 (Timer underflow) •...
Page 107: Adc Conversion Result Buffer Register
Analog-to-Digital Converter ADC Conversion Result Buffer Register ADC Conversion Result Buffer Register ADC Conversion Result Buffer Register ADCRESULT0 @ 0x007108 through ADCRESULT15 @ 0x007117 ADCRESULT0 @ 0x007108 through ADCRESULT15 @ 0x007117 (lab file: (lab file: (Total of 16 Registers) (Total of 16 Registers) With analog input 0V to 3V, we have: With analog input 0V to 3V, we have: analog volts...
Page 108: Numerical Format
Analog-to-Digital Converter Numerical Format How do we Read the Result? How do we Read the Result? Integer format Integer format RESULTx RESULTx bit shift right bit shift right Data Data Example: read RESULT0 register Example: read RESULT0 register #include "DSP281x_Device.h" #include "DSP281x_Device.h"...
Page 109: Lab 6: Analog-To-Digital Converter
Lab 6: Analog-to-Digital Converter Lab 6: Analog-to-Digital Converter Objective The objective of this lab is to apply the techniques discussed in module 6 and to become familiar with the programming and operation of the on-chip analog-to-digital converter. The DSP will be setup to sample a single ADC input channel at a prescribed sampling rate and store the conversion result in a buffer in the DSP memory.
Page 110 Lab 6: Analog-to-Digital Converter toggles a GPIO pin (GPIOA1) high and low in the ADC interrupt service routine. The ADC ISR will also toggle LED DS2 on the eZdsp™ as a visual indication that the ISR is running. This pin will be connected to the ADC input pin, and sampled.
Page 111 Lab 6: Analog-to-Digital Converter Main_6.c Labcfg.cmd Lab.cdb DSP281x_Headers_BIOS.cmd User_5_6_7.cmd CodeStartBranch.asm SysCtrl.c Gpio.c DSP281x_GlobalVariableDefs.c PieCtrl_5_6_7_8_9.c DefaultIsr_5_6_7.c Adc.c Ev_6.c Setup ADC Initialization and Enable Core/PIE Interrupts 2. In Main_6.c add code to call InitAdc() and InitEv() functions. The InitEv() function is used to configure Timer 2 to trigger the ADC at a 50 kHz rate. Details about the event manager will be discussed in the next module.
Page 112 Lab 6: Analog-to-Digital Converter Run the Code 10. In Main_6.c place the cursor in the “main loop” section, right click on the mouse key and select Run To Cursor. 11. Open a memory window to view some of the contents of the ADC results buffer. The address label for the ADC results buffer is AdcBuf.
Page 113 Lab 6: Analog-to-Digital Converter 17. Recall that the program toggled the IOPA1 pin at a 50 kHz rate. Therefore, a complete cycle (toggle high, then toggle low) occurs at half this rate, or 25 kHz. We therefore expect the period of the waveform to be 40 µs. Confirm this by measuring the period of the saw-tooth wave using the graph (you may want to enlarge the graph window using the mouse).
Page 114 Lab 6: Analog-to-Digital Converter 21. Run the code and watch the windows update in real-time mode. Are the values updating as expected? 22. Fully halting the DSP when in real-time mode is a two-step process. First, halt the processor with Debug Halt.
Page 115 Event Manager Introduction This module explains how to generate PWM waveforms using the timers and compare units. Also, the capture units, quadrature encoder pulse circuit, and the hardware deadband units will be discussed. All devices of the C28x family have two event managers, EVA and EVB. These two event managers are identical to each other in terms of functionality.
Page 116 Module Topics Module Topics Event Manager ............................7-1 Module Topics............................7-2 Event Manager............................7-3 PWM Review............................7-4 General-Purpose Timers......................... 7-8 GP Timer Modes of Operation ......................7-10 GP Timer Registers ...........................7-12 Asymmetric and Symmetric PWM via General Purpose Timer Compares........7-16 GP Timer Compare PWM Exercise ....................7-17 Compare Units ............................7-18 Compare Unit Registers........................7-19 Hardware Dead-Band (Compare Units only) ..................7-22...
Page 117: Event Manager
Event Manager Event Manager Event Manager Block Diagram Event Manager Block Diagram (EVA) (EVA) Reset Reset TCLKINA / TDIRA TCLKINA / TDIRA EV Control Registers / Logic EV Control Registers / Logic ADC Start ADC Start GP Timer 1 Compare Output Logic GP Timer 1 Compare Output Logic...
Page 118: Pwm Review
PWM Review PWM Review What is Pulse Width Modulation? What is Pulse Width Modulation? PWM is a scheme to represent a signal PWM is a scheme to represent a signal as a sequence of pulses as a sequence of pulses fixed carrier frequency fixed carrier frequency fixed pulse amplitude...
Page 119 PWM Review PWM Signal Representation PWM Signal Representation Original Signal Original Signal same areas (energy) same areas (energy) PWM representation PAM representation PWM representation PAM representation Why Use PWM in Digital Motor Control? Why Use PWM in Digital Motor Control? Desired motor phase currents or voltages are Desired motor phase currents or voltages are known...
Page 120 PWM Review Asymmetric PWM Waveform Asymmetric PWM Waveform Period Period Compare Compare Counter Counter Caused by Period match Caused by Period match (active high) (active high) (toggle output in Asym mode only) (toggle output in Asym mode only) Caused by Compare match Caused by Compare match 7 - 6 C28x - Event Manager...
Page 121 PWM Review Symmetric PWM Waveform Symmetric PWM Waveform Period Period Compare Compare Counter Counter (active high) (active high) Interrupts Interrupts General Purpose Timer Full Compare Units PWM1 Compare Period PWM2 PWM3 Compare Compare PWM4 Compare PWM5 Counter PWM6 Each C28x event manager (EVA and EVB) is capable of generating five independent PWM signals.
Page 122 General-Purpose Timers General-Purpose Timers General Purpose Timers General Purpose Timers (EVA) (EVA) Reset Reset TCLKINA / TDIRA TCLKINA / TDIRA EV Control Registers / Logic EV Control Registers / Logic ADC Start ADC Start GP Timer 1 Compare Output Logic GP Timer 1 Compare Output Logic T1PWM_T1CMP...
Page 123 General-Purpose Timers General Purpose Timer Block Diagram General Purpose Timer Block Diagram (EVA) (EVA) Internal Internal TxCMPR . 15 TxCMPR . 15 (HSPCLK) (HSPCLK) TPS 2 TPS 2 Shadowed Shadowed Clock Clock TxCON . 10 TxCON . 10 Compare Compare Prescaler Prescaler Register...
Page 124: Gp Timer Modes Of Operation
General-Purpose Timers GP Timer Modes of Operation The C28x event managers (EVA and EVB) each have two General Purpose Timers (GP Timers). Each timer has four different modes of operation. The most simple is the Stop/Hold mode, where the operation of the timer stops and holds at its current state. The timer counter, its compare output, and its prescale counter all remain unchanged in this mode.
Page 125 General-Purpose Timers Continuous-Up/Down Counting Continuous Up/Down Counting Mode Continuous Up/Down Counting Mode (Used for Symmetric PWM Waveforms) (Used for Symmetric PWM Waveforms) This example: This example: TxCON.3 2 = 01 (reload TxCMPR on underflow or period match) TxCON.3 2 = 01 (reload TxCMPR on underflow or period match) TxPR...
Page 126: Gp Timer Registers
General-Purpose Timers PWM Outputs and Interrupts Generated Outputs and Interrupts Generated Outputs and Interrupts PWM period #2 PWM period #2 New Period is New Period is CPU Changes CPU Changes Auto loaded on Auto loaded on Period Reg. Buffer Period Reg. Buffer Underflow here Underflow here anytime here...
Page 127 General-Purpose Timers GP Timer Registers GP Timer Registers (lab file: (lab file: Register Address Description Register Address Description GPTCONA 0x007400 General Purpose Timer Control Register A T1CNT 0x007401 Timer 1 Counter Register T1CMPR 0x007402 Timer 1 Compare Register Buffer T1PR 0x007403 Timer 1 Period Register Buffer T1CON...
Page 128 General-Purpose Timers GP Timer Control Register A GP Timer Control Register A (EVA) (EVA) GPTCONA @ 0x007400 GPTCONA @ 0x007400 (lab file: (lab file: Lower Byte: Lower Byte: Timer 2 Compare Output Enable Timer 1 Compare Output Enable Timer 2 Compare Output Enable Timer 1 Compare Output Enable T2CMPOE T2CMPOE...
Page 129 General-Purpose Timers Timer Control Register Timer Control Register (EVA) (EVA) T1CON @ 0x007404 / T2CON @ 0x007408 T1CON @ 0x007404 / T2CON @ 0x007408 (lab file: (lab file: Timer Compare Operation Enable Timer Compare Operation Enable Lower Byte: Lower Byte: 0 = disable 0 = disable 1 = enable...
Page 130: Asymmetric And Symmetric Pwm Via General Purpose Timer Compares
General-Purpose Timers Asymmetric and Symmetric PWM via General Purpose Timer Compares PWM switching frequency: The PWM carrier frequency is determined by the value contained in the period register TxPR, and the frequency of the clocking signal. The value needed in the period register is: ...
Page 131: Gp Timer Compare Pwm Exercise
General-Purpose Timers GP Timer Compare PWM Exercise GP Timer Compare PWM Exercise GP Timer Compare PWM Exercise Symmetric PWM is to be generated as follows: Symmetric PWM is to be generated as follows: • • 50 kHz carrier frequency 50 kHz carrier frequency •...
Page 132 Compare Units Compare Units Compare Units Compare Units (EVA) (EVA) Reset Reset TCLKINA / TDIRA TCLKINA / TDIRA EV Control Registers / Logic EV Control Registers / Logic ADC Start ADC Start GP Timer 1 Compare Output Logic GP Timer 1 Compare Output Logic T1PWM_T1CMP T1PWM_T1CMP...
Page 133: Compare Unit Registers
Compare Units Compare Unit Registers Compare Unit Registers Compare Unit Registers (lab file: (lab file: Register Register Address Address Description Description COMCONA 0x007411 Compare Control Register A COMCONA 0x007411 Compare Control Register A ACTRA 0x007413 Compare Action Control Register A ACTRA 0x007413 Compare Action Control Register A...
Page 134 Compare Units Compare Control Register Compare Control Register (EVA) (EVA) COMCONA @ 0x007411 COMCONA @ 0x007411 (lab file: (lab file: Lower Byte: Lower Byte: Full Compare 2 Full Compare 2 Full Compare 2 Full Compare 2 Output Enable Trip Enable Output Enable Trip Enable FCMP2OE...
Page 135 Compare Units Compare Action Control Register Compare Action Control Register (EVA) (EVA) ACTRA @ 0x007413 ACTRA @ 0x007413 (lab file: (lab file: Basic Space Vector Bits can write as 0 when SV not in use SVRDIR CMP6ACT1 CMP6ACT0 CMP5ACT1 CMP5ACT0 CMP4ACT1 CMP4ACT0 CMP3ACT1 CMP3ACT0 CMP2ACT1 CMP2ACT0...
Page 136: Hardware Dead-Band (Compare Units Only)
Compare Units Hardware Dead-Band (Compare Units only) Motivation for Dead Band Motivation for Dead Band supply rail Gate Signals are to motor phase Complementary PWM ♦ Transistor gates turn on faster than they shut off ♦ Short circuit if both gates are on at same time! Dead-band control provides a convenient means of combating current shoot-through problems in a power converter.
Page 137 Compare Units Dead Band Functionality Dead Band Functionality (EVA) (EVA) Prescaler Clock HSPCLK DBTCONA . 4 - 2 edge detect 4-bit Counter reset DTPH comparator DTPH 4-bit period DBTCONA . 11 - 8 dead time DTPH Asymmetric PWM Example DTPH Two basic approaches exist for controlling shoot-through: modify the transistors, or modify the PWM gate signals controlling the transistors.
Page 138 Compare Units precise control of gate timing requirements. In addition, the dead time is typically specified with a single program variable that is easily changed for different power converters or adapted on-line. Dead Band Timer Control Register Dead Band Timer Control Register (EVA) (EVA) DBTCONA @ 0x007415...
Page 139: Power Drive Protection
Compare Units Power Drive Protection The PDPINTx is a safety feature that is provided for the safe operation of systems such as power converters and motor drives. PDPINTx can be used to inform the monitoring program of motor drive abnormalities such as overvoltage, over-current, and excessive temperature rise. If the PDPINTx interrupt is unmasked, all PWM output pins will be put in the high-impedance state immediately after the PDPINTx pin is driven low.
Page 140 Capture Units Capture Units Capture Units Capture Units (EVA) (EVA) Reset TCLKINA / TDIRA EV Control Registers / Logic ADC Start GP Timer 1 Compare Output Logic T1PWM_T1CMP GP Timer 1 • PWM1 Compare Unit 1 PWM Circuits Output Logic PWM2 PWM3 Compare Unit 2...
Page 141: Capture Units
Capture Units Capture Units Capture Units Timer Trigger Timestamp Values Capture units timestamp transitions on Capture units timestamp transitions on capture input pins capture input pins Three capture units (per event manager) Three capture units (per event manager) each associated with a capture input pin each associated with a capture input pin The capture units allow time-based logging of external TTL signal transitions on the capture input pins.
Page 142 Capture Units Some Uses for the Capture Units Some Uses for the Capture Units ♦ Synchronized ADC start with capture event ♦ Measure the time width of a pulse ♦ Low speed velocity estimation from incr. encoder: Problem: At low speeds, calculation of ≈...
Page 143 Capture Units Capture Unit FIFO Operation Capture Unit FIFO Operation CPU can read both upper and lower FIFO registers CPU can read both upper and lower FIFO registers separately; Standard approach is to read upper, but separately; Standard approach is to read upper, but lower can be read lower can be read value #2...
Page 144 Capture Units The capture unit interrupts offer immediate CPU notification of externally captured events. In situations where this is not required, the interrupts can be masked and flag testing/polling can be used instead. This offers increased flexibility for resource management. For example, consider a servo application where a capture unit is being used for low-speed velocity estimation via a pulsing sensor.
Page 145 Capture Units Capture FIFO Status Register Capture FIFO Status Register (EVA) (EVA) CAPFIFOA @ 0x007422 CAPFIFOA @ 0x007422 (lab file: (lab file: 15-14 13-12 11-10 CAP3FIFO CAP2FIFO CAP1FIFO reserved reserved FIFOx Status: CAPxFIFO bits are 00 = empty automatically adjusted on a 01 = one entry capture or FIFO read 10 = two entries...
Page 146: Quadrature Encoder Pulse (Qep)
Quadrature Encoder Pulse (QEP) Quadrature Encoder Pulse (QEP) Quadrature Encoder Pulse Quadrature Encoder Pulse (EVA) (EVA) Reset TCLKINA / TDIRA EV Control Registers / Logic ADC Start GP Timer 1 Compare Output Logic T1PWM_T1CMP GP Timer 1 • PWM1 Compare Unit 1 PWM Circuits Output Logic PWM2...
Page 147 Quadrature Encoder Pulse (QEP) What is an Incremental Quadrature What is an Incremental Quadrature Encoder? Encoder? A digital (angular) position sensor A digital (angular) position sensor photo sensors spaced θ/4 deg. apart slots spaced θ deg. apart θ/4 light source (LED) θ...
Page 148: Qep Initialization With Gp Timer 2 (Eva)
Quadrature Encoder Pulse (QEP) Incremental Encoder Connections (EVA) Incremental Encoder Connections (EVA) Ch. A Ch. B CAP1/QEP1 decoder CAP2/QEP2 logic Index GP Timer 2 selected as GP Timer 2 selected as QEPIQUAL pulse counter pulse counter Timer Timer Prescaler Prescaler bypassed (i.e.
Page 149 Quadrature Encoder Pulse (QEP) Extension Control Register A Extension Control Register A (EVA) (EVA) EXTCONA @ 0x007409 EXTCONA @ 0x007409 (lab file: (lab file: Independent Compare QEP Index Enable Output Enable Mode 0 = disable 0 = disable 1 = enable 1 = enable 15-4 reserved...
Page 150: Lab 7: Event Manager
Lab 7: Event Manager Lab 7: Event Manager Objective The objective of this lab is to apply the techniques discussed in module 7 and become familiar with the programming and operation of the Event Manager and its interrupts. General-Purpose Timer 1 and Compare 1 will be setup to generate a 2 kHz, 25% duty cycle symmetric PWM waveform.
Page 151 Lab 7: Event Manager Main_7.c Labcfg.cmd Lab.cdb DSP281x_Headers_BIOS.cmd User_5_6_7.cmd CodeStartBranch.asm SysCtrl.c Gpio.c DSP281x_GlobalVariableDefs.c PieCtrl_5_6_7_8_9.c DefaultIsr_5_6_7.c Adc.c Ev_7_8_9_10.c Setup Shared I/O, General-Purpose Timer1 and Compare1 2. Edit Gpio.c and adjust the shared I/O pins in Group A for the PWM1 function. 3.
Page 152 Lab 7: Event Manager Start Address AdcBuf Acquisition Buffer Size Display Data Size DSP Data Type 16-bit unsigned integer Sampling Rate (Hz) 50000 µ s Time Display Unit Select OK to save the graph options. 10. The graphical display should show the generated 2 kHz, 25% duty cycle symmetric PWM waveform.
Page 153 Lab 7: Event Manager 13. Fully halt the DSP (real-time mode) by using Debug Halt and then unchecking the “Real-time mode” . Setup Capture Unit 1 to Measure Width of Pulse 14. Edit Gpio.c and adjust the shared I/O pins in Group A for the CAP1 function. 15.
Page 154 Lab 7: Event Manager 24. Run the code in real-time mode. Notice the values for CAP_rising and CAP_falling (ignore the CAP_duty value until step 25). Then fully halt the DSP. Questions: • Which GP Timer is being used to clock the PWM1? •...
Page 155 Lab 7: Event Manager Run the Code – Duty Cycle Measurement 29. Be sure that the memory window is open to view the address label CAP_duty . (Use &CAP_duty in address box). 30. With the wire still connecting the PWM1 (pin # P8-9) to CAP1 (pin # P8-6) on the eZdsp™, run (real-time mode) the code again, and fully halt it after a few seconds.
Page 156: Gp Timer Compare Pwm Exercise Solution
GP Timer Compare PWM Exercise Solution GP Timer Compare PWM Exercise Solution GP Timer Compare PWM Exercise GP Timer Compare PWM Exercise Solution Solution GPTCONA = GPTCONA = (xxx0000001000010)b (xxx0000001000010)b 0042h 0042h (all (all x’s x’s assigned a value of 0) assigned a value of 0) T1CON = T1CON =...
Page 157 Numerical Concepts & IQmath Introduction In this module, numerical concepts will be explored. One of the first considerations concerns multiplication – how does the user store the results of a multiplication, when the process of mul- tiplication creates results larger than the inputs. A similar concern arises when considering accu- mulation –...
Page 158 Module Topics Module Topics Numerical Concepts & IQmath ....................... 8-1 Module Topics............................8-2 Numbering System Basics ........................8-3 Binary Numbers..........................8-3 Two's Complement Numbers ......................8-3 Sign Extension Mode.......................... 8-5 Binary Multiplication..........................8-6 Binary Fractions ............................. 8-8 Representing Fractions in Binary ....................... 8-8 Multiplying Binary Fractions ......................
Page 159: Numbering System Basics
Numbering System Basics Numbering System Basics Given the ability to perform arithmetic processes (addition and multiplication) with the C28x, it is important to understand the underlying mathematical issues which come into play. Therefore, we shall examine the numerical concepts which apply to the C28x and, to a large degree, most processors.
Page 160 Numbering System Basics To load small two's complement numbers into larger registers: The MSB of the original number must carry to the MSB of the number when represented in the larger register. 1. Load the small number “right justified” into the larger register. 2.
Page 161: Sign Extension Mode
Numbering System Basics Sign Extension Mode The C28x can operate on either unsigned binary or two's complement operands. The “Sign Extension Mode” (SXM) bit, present within a status register of the C28x, identifies whether or not the sign extension process is used when a value is brought into the accumulator. It is good programming practice to always select the desired SXM at the beginning of a module to assure the proper mode.
Page 162: Binary Multiplication
Binary Multiplication Binary Multiplication Now that you understand two's complement numbers, consider the process of multiplying two two's complement values. As with “long hand” decimal multiplication, we can perform binary multiplication one “place” at a time, and sum the results together at the end to obtain the total product.
Page 163 Binary Multiplication Note: With two’s complement multiplication, the leading “1” in the second multiplicand is a sign bit. If the sign bit is “1”, then take the 2’s complement of the first multiplicand. Additionally, each partial product must be sign-extended for correct computation. Note: All of the above questions except the final one are addressed in this module.
Page 164: Binary Fractions
Binary Fractions Binary Fractions Given the problems associated with integers and multiplication, consider the possibilities of using fractional values. Fractions do not grow when multiplied, therefore, they remain representable within a given word size and solve the problem. Given the benefit of fractional multiplication, consider the issues involved with using fractions: •...
Page 165: Multiplying Binary Fractions
Binary Fractions Multiplying Binary Fractions When the C28x performs multiplication, the process is identical for all operands, integers or fractions. Therefore, the user must determine how to interpret the results. As before, consider the 4-bit multiply example: Four Bit Multiplication Four Bit Multiplication 0100...
Page 166 Binary Fractions As with integers, the results are loaded low, and the MSB is a sign extension of the seventh bit. If this value were loaded into the accumulator, we could store the results back to memory in a variety of ways: •...
Page 167: Fraction Coding
Fraction Coding Fraction Coding Although COFF tools recognize values in integer, hex, binary, and other forms, they understand only integer, or non-fractional values. To use fractions within the C28x, it is necessary to describe them as though they were integers. This turns out to be a very simple trick. Consider the following number lines: How is a fraction coded? How is a fraction coded?
Page 168: Fractional Vs. Integer Representation
Fractional vs. Integer Representation Fractional vs. Integer Representation Fractional vs. Integer Fractional vs. Integer Range Range Integers have a maximum range Integers have a maximum range determined by the number of bits determined by the number of bits Fractions have a maximum range of ±1 Fractions have a maximum range of ±1 Precision Precision...
Page 169: Iqmath
IQmath IQmath Implementing complex digital control algorithms on a Digital Signal Processor (DSP), or any other DSP capable processor, typically come across the following issues: • Algorithms are typically developed using floating-point math • Floating-point devices are more expensive than fixed-point devices •...
Page 170: Floating-Point Representation
IQmath Floating-Point Representation IEEE Std. 754 Single Precision IEEE Std. 754 Single Precision Floating Point Floating Point 31 30 23 22 s eeeeeeee fffffffffffffffffffffff 1 bit sign 8 bit exponent 23 bit mantissa (fraction) Case 1: if e = 255 and f = 0, then v = NaN Case 2: if e = 255 and f = 0,...
Page 171: Iq Fractional Representation
IQmath IQ Fractional Representation A new approach to fixed-point algorithm development, termed “IQmath”, can greatly simplify the design development task. This approach can also be termed “virtual floating-point” since it looks like floating-point, but it is implemented using fixed-point techniques. IQ Fractional Representation IQ Fractional Representation S IIIIIIII fffffffffffffffffffffff...
Page 172 IQmath IQmath Can Solve the Problem! IQmath Can Solve the Problem! I8Q24 Example: x = 10.0 (0x0C000000) + y = 0.000000238 (0x00000002) z = 10.000000238 (0x0C000002) Exact Result (this example) 8 - 16 C28x - Numerical Concepts & IQmath...
Page 173: Traditional "Q" Math Approach
IQmath Traditional “Q” Math Approach Traditional 16 bit “Q” Math Approach Traditional 16 bit “Q” Math Approach sssssssssssss Align Binary << 15 Point For Add Align Binary >> 15 Point For Store ssssssssssssI in C: Y = ((i32) M * (i32) X + (i32) B << Q) >> Q; Traditional 32 bit “Q”...
Page 174 IQmath The traditional approach to performing math operations, using fixed-point numerical techniques can be demonstrated using a simple linear equation example. The floating-point code for a linear equation would be: float Y, M, X, B; Y = M * X + B; For the fixed-point implementation, assume all data is 32-bits, and that the "Q"...
Page 175 IQmath IQmath Approach IQmath Approach IQmath Approach Align Decimal >> 24 Point Of Multiply sssssssssssssssssI16 in C: Y = ((i64) M * (i64) X) >> Q + B; In the "IQmath" approach, rather then scaling the operands, which get added to or subtracted from the multiplication result, we do the reverse.
Page 176 IQmath Using the operator overloading features of C++, we can overload the multiplication operand "*" such that when a particular data type is encountered, it will automatically implement the scaled multiply operation. Lets define a data type called "iq" and assign the linear variables to this data type: iq Y, M, X, B // numbers are all Q24 The overloading of the multiply operand in C++ can be defined as follows:...
Page 177: Iqmath Approach
IQmath IQmath Approach IQmath Approach Multiply Operation Multiply Operation Y = ((i64) M * (i64) X) >> Q + B; Redefine the multiply operation as follows: Redefine the multiply operation as follows: _IQmpy(M,X) == ((i64) M * (i64) X) >> Q This simplifies the equation as follows: This simplifies the equation as follows: Y = _IQmpy(M,X) + B;...
Page 178 IQmath IQmath Approach IQmath Approach GLOBAL_Q simplification GLOBAL_Q simplification User selects “Global Q” value for the whole application User selects “Global Q” value for the whole application GLOBAL_Q GLOBAL_Q based on the required dynamic range or resolution, for example: based on the required dynamic range or resolution, for example: GLOBAL_Q GLOBAL_Q Max Val...
Page 179 IQmath IQmath Approach IQmath Approach Targeting Fixed Point or Floating Point device Targeting Fixed Point or Floating Point device Y = _IQmpy(M, X) + B; User selects target math type (in “IQmathLib.h” file) #if MATH_TYPE == IQ_MATH #if MATH_TYPE == FLOAT_MATH Y = (float)M * (float)X + (float)B;...
Page 180: Iqmath Library
IQmath Library IQmath Library IQmath Library: IQmath Library: math & trig functions (v1.4) math & trig functions (v1.4) Operation Floating Point “IQmath” in C “IQmath” in C++ Operation Floating Point “IQmath” in C “IQmath” in C++ type type float A, B; float A, B;...
Page 181 IQmath Library 16-Bit vs. 32-Bit The "IQmath" approach could also be used on 16 bit sized numbers and for many problems, this is sufficient resolution. However, in many control cases, the user needs to use many different "Q" values to accommodate the limited resolution of a 16-bit number. With DSP devices like the TMS320C28x processor, which can perform 16 bit and 32 bit sized math with equal efficiency, the choice becomes more of productivity (time to market).
Page 182: Ac Induction Motor Example
AC Induction Motor Example AC Induction Motor Example AC Induction Motor Example AC Induction Motor Example One of the more complex motor control algorithms One of the more complex motor control algorithms Sensorless , ACI induction machine direct rotor flux control Sensorless , ACI induction machine direct rotor flux control Goal: motor speed estimation &...
Page 183 AC Induction Motor Example The next few slides shows the coding of one particular block, PARK Transform, using floating- point and "IQmath" approaches in C and C++: AC Induction Motor Example AC Induction Motor Example Park Transform Park Transform floating floating point C code point C code...
Page 184 AC Induction Motor Example AC Induction Motor Example AC Induction Motor Example Park Transform converting to “ IQmath ” C++ code Park Transform converting to “ IQmath ” C++ code #include #include “ “ math.h” math.h ” extern “C” { #include “IQmathLib.h” } #include “IQmathCPP.h”...
Page 185 AC Induction Motor Example The code was compiled and run on the Texas Instruments TMS320C28x fixed-point DSP device (IQ_MATH mode) and on the TMS320C3x floating-point DSP device (FLOAT_MATH mode). The plots of speed and stator current for both devices matched and are shown below.
Page 186 AC Induction Motor Example AC Induction Motor Example AC Induction Motor Example GLOBAL_Q = 27, system unstable GLOBAL_Q = 27, system unstable IQmath: speed IQmath: current AC Induction Motor Example AC Induction Motor Example GLOBAL_Q = 16, system unstable GLOBAL_Q = 16, system unstable IQmath: speed IQmath: current 8 - 30...
Page 187 AC Induction Motor Example With the ability to select the GLOBAL_Q value for all calculations in the "IQmath", an experi- ment was conducted to see what maximum and minimum Q value the system could tolerate be- fore it became unstable. The results are tabulated in the slide below: AC Induction Motor Example AC Induction Motor Example Q stability range...
Page 188 AC Induction Motor Example AC Induction Motor Example AC Induction Motor Example Performance comparisons Performance comparisons C28x C C28x C C3x C C3x C C67x C C67x C C67x C C67x C IQmath IQmath float float ( float float ( float (no float (no –...
Page 189: Iqmath Appications And Summary
IQmath Appications and Summary IQmath Appications and Summary Where Is IQmath Applicable? Where Is IQmath Applicable? Anywhere a large dynamic range is not required Motor Control (PID, State Estimator, Kalman,...) Servo Control Modems Audio (MP3, etc.) Imaging (JPEG, etc.) Any application using 16/32-bit fixed-point Q math Where it is not applicable Graphical applications (3D rotation, etc.) When trying to squeeze every last cycle...
Page 190 IQmath Appications and Summary The IQmath approach, matched to a fixed-point processor with 32x32 bit capabilities enables the following: • Seamless portability of code between fixed and floating-point devices • Maintenance and support of one source code set from simulation to target device •...
Page 191: Converting Adc Results Into Iq Format
Converting ADC Results into IQ Format Converting ADC Results into IQ Format As you may recall, the converted values of the ADC are placed in the upper 12 bit of the RESULT0 register. Before these values are filtered using the IQmath library, they need to to be put into the IQ format as a 32-bit long.
Page 192: Lab 8: Iqmath Fir Filter
Lab 8: IQmath FIR Filter Lab 8: IQmath FIR Filter Objective The objective of this lab is to apply the techniques discussed in module 8 and to become familiar with IQmath programming. In the previous lab, General-Purpose Timer 1 and Compare 1 from Event Manager A (EVA) were setup to generate a 2 kHz, 25% duty cycle symmetric PWM waveform.
Page 193 Lab 8: IQmath FIR Filter Main_8.c Labcfg.cmd Lab.cdb DSP281x_Headers_BIOS.cmd User_8_9.cmd CodeStartBranch.asm SysCtrl.c Gpio.c DSP281x_GlobalVariableDefs.c PieCtrl_5_6_7_8_9.c DefaultIsr_8.c Adc.c Ev_7_8_9_10.c Filter.c Project Build Options 2. Setup the include search path to include the IQmath header file. Open the Build Options and select the Compiler tab. In the Preprocessor Category, find the Include Search Path (-i) box and add to the end of the line (preceeded with a semicolon to append this directory to the existing search path): ;c:\tidcs\c28\IQmath\cIQmath\include...
Page 194 Lab 8: IQmath FIR Filter Select a Global IQ value 6. Open the file c:\tidcs\c28\IQmath\cIQmath\include\IQmathLib.h. Confirm that the GLOBAL_Q type (near beginning of file) is set to a value of 24. If it is not, modify as necessary: #define GLOBAL_Q Recall that this Q type will provide 8 integer bits and 24 fractional bits.
Page 195 Lab 8: IQmath FIR Filter Display Type Dual Time Start Address – upper display AdcBufFiltered Start Address – lower display AdcBuf Acquisition Buffer Size Display Data Size DSP Data Type 32-bit signed integer Q-value Sampling Rate (Hz) 50000 µs Time Display Unit Select OK to save the graph options.
Page 196 Lab 8: IQmath FIR Filter Lab 8 Reference: IQmath FIR Filter Bode Plot of Digital Low Pass Filter Coefficients: [1/16, 4/16, 6/16, 4/16, 1/16] Sample Rate: 50 kHz 8 - 40 C28x - Numerical Concepts & IQmath...
Page 197 Using DSP/BIOS Introduction This module discusses the basic features of using DSP/BIOS in a system. Scheduling threads, periodic functions, and the use of real-time analysis tools will be demonstrated. Learning Objectives Learning Objectives Learning Objectives Introduction to DSP/BIOS Introduction to DSP/BIOS Scheduling DSP/BIOS threads Scheduling DSP/BIOS threads Periodic Functions...
Page 198 Module Topics Module Topics Using DSP/BIOS............................9-1 Module Topics............................9-2 Introduction to DSP/BIOS ........................9-3 Scheduling DSP/BIOS Threads....................... 9-5 Periodic Functions..........................9-12 Real-time Analysis Tools........................9-13 DSP/BIOS API Module and Summary ....................9-14 Lab 9: DSP/BIOS...........................9-15 9 - 2 C28x - Using DSP/BIOS...
Page 199: Introduction To Dsp/Bios
Introduction to DSP/BIOS Introduction to DSP/BIOS Introduction to DSP/BIOS Introduction to DSP/BIOS What is DSP/BIOS? What is DSP/BIOS? A full A full featured, scalable real featured, scalable real time kernel time kernel System configuration tools System configuration tools Preemptive multi threading scheduler Preemptive multi threading scheduler...
Page 200 Introduction to DSP/BIOS DSP/BIOS Terminology DSP/BIOS Terminology thread a path of program execution thread a path of program execution scheduler a program that manages threads scheduler a program that manages threads preemption the act of a higher priority thread preemption the act of a higher priority thread interrupting a lower priority thread interrupting a lower priority thread...
Page 201: Scheduling Dsp/Bios Threads
Scheduling DSP/BIOS Threads Scheduling DSP/BIOS Threads Problem: Add a Function to your Code Problem: Add a Function to your Code Existing Function Function 1 New Function Function 2 Issues: Do we have enough bandwidth (MIPS)? TI DSP Will one routine conflict with the other? How is a compound system created? What are some possible solutions? Possible Solution Using while Loop...
Page 202 Scheduling DSP/BIOS Threads Possible Solution Using Interrupts Possible Solution Using Interrupts An interrupt driven system places main each function in its own ISR while(1); Period Compute CPU Usage 1 µs Function 1: 0.05 ms 3 µs Function 2: 500 ms ~ 0% Function1_ISR Function 1...
Page 203 Scheduling DSP/BIOS Threads HWI Dispatcher for ISRs HWI Dispatcher for ISRs For non-BIOS code, we use the interrupt keyword to declare an ISR tells the compiler to perform context save/restore interrupt void MyHwi(void) For DSP/BIOS code, the dispatcher will perform the save/restore Remove the interrupt keyword from the MyHwi() Check the “Use Dispatcher”...
Page 204 Scheduling DSP/BIOS Threads SWI Properties SWI Properties Managing SWI Priority Managing SWI Priority Drag and Drop SWIs to change Drag and Drop SWIs to change priority priority Equal priority SWIs run in the Equal priority SWIs run in the order that they are posted order that they are posted 9 - 8 C28x - Using DSP/BIOS...
Page 205 Scheduling DSP/BIOS Threads Priority Based Thread Scheduling Priority Based Thread Scheduling post3 rtn HWI 2 SWI_post(&swi2); (highest) post2 rtn HWI 1 post1 SWI 3 int2 SWI 2 SWI 1 MAIN int1 IDLE (lowest) User sets the priority...BIOS does the scheduling Another Solution –...
Page 206 Scheduling DSP/BIOS Threads SWIs TSKs SWIs TSKs SWI_post SEM_post start SEM_pend Pause “run to (blocked state) completion” start Similar to hardware interrupt, SEM_post() readies the TSK but triggered by SWI_post() which pends on an event All SWI's share system The event triggers the TSK software stack to run once and pend Each TSK has its own stack,...
Page 207 Scheduling DSP/BIOS Threads Enabling BIOS – Return from main() Enabling BIOS – Return from main() main Must delete the endless while() loop { … main() returns to BIOS IDLE thread, // return to BIOS allowing BIOS to schedule events, transfer info to host, etc. An endless while() loop in main() will not allow BIOS to activate DSP BIOS...
Page 208: Periodic Functions
Periodic Functions Periodic Functions Periodic Functions Periodic Functions tick DSP/BIOS period Periodic functions run at a specific rate in your system: - e.g. LED blink requires 0.5 Hz Use the CLK Manager to specify the DSP/BIOS CLK rate in microseconds per “tick” Use the PRD Manager to specify the period (for the function) in ticks Allows multiple periodic functions with different rates Creating a Periodic Function...
Page 209: Real-Time Analysis Tools
Real-time Analysis Tools Real-time Analysis Tools Built in Real Time Analysis Tools Built in Real Time Analysis Tools Gather data on target (3-10 CPU cycles) Send data during BIOS IDL (100s of cycles) Format data on host (1000s of cycles) Data gathering does NOT stop target CPU Execution Graph Software logic analyzer...
Page 210: Dsp/Bios Api Module And Summary
DSP/BIOS API Module and Summary DSP/BIOS API Module and Summary DSP/BIOS API Modules DSP/BIOS API Modules TSK Communication/Synchronization TSK Communication/Synchronization Instrumentation/Real Time Analysis Instrumentation/Real Time Analysis Semaphores manager Semaphores manager Message log manager Message log manager Mailboxes manager Mailboxes manager Statistics accumulator manager Statistics accumulator manager Resource lock manager...
Page 211 Lab 9: DSP/BIOS Lab 9: DSP/BIOS Objective The objective of this lab is to apply the techniques discussed in module 9 and to become familiar with DSP/BIOS. In this lab exercise, we are going to change the ADCINT_ISR HWI to a SWI. Then, we will replace the LED blink routine with a Periodic Function.
Page 212 Lab 9: DSP/BIOS Main_9.c Labcfg.cmd Lab.cdb DSP281x_Headers_BIOS.cmd User_8_9.cmd CodeStartBranch.asm SysCtrl.c Gpio.c DSP281x_GlobalVariableDefs.c PieCtrl_5_6_7_8_9.c DefaultIsr_9_10.c Adc.c Ev_7_8_9_10.c Filter.c Add a SWI to main.c 2. Open Main_9.c and notice that space has been added at the end of main() for two new functions which will be used in this module –...
Page 213 Lab 9: DSP/BIOS Post a SWI 8. In DefaultIsr_9_10.c add the following SWI_post to the ADCINT_ISR(), just after the structure used to acknowledge the PIE group: SWI_post(&ADC_swi); // post a SWI This post a SWI that will execute the ADC_swi() code you populated a few steps back in the lab.
Page 214 Lab 9: DSP/BIOS Run the Code – AdcSwi() 15. We will be running our code in real-time mode, and need to have our window continuously refresh. Enable Real-time Mode and be sure that the Global Continuous Refresh option has been checked. Note: For the next step, check to be sure that the jumper wire connecting “VREFLO”...
Page 215 Lab 9: DSP/BIOS 20. Open DefaultIsr_9_10.c and locate the ADCINT_ISR routine. Move the instruction used to toggle the LED to the LedBlink() function in Main_9.c: GpioDataRegs.GPFTOGGLE.bit.GPIOF14 = 1; // Toggle the pin 21. In the configuration file Lab.cdb we need to add and setup the LedBlink_PRD. Open Lab.cdb and click on the plus sign (+) to the left of Scheduling.
Page 216 Lab 9: DSP/BIOS 27. Next, open the execution graph. On the menu bar click: DSP/BIOS Execution Graph The execution graph is a special graph used to display information about different threads in the system and when they occur relative to the other events. This graph is not based on time, but the activity of events (i.e.
Page 217 Lab 9: DSP/BIOS The message log dialog box is displaying the number of times (count value) that AdcSwi() has executed. 36. Run the DSP. 37. Observe the operation of the various windows that are open, and the information that they are conveying in real-time.
Page 218 Lab 9: DSP/BIOS 9 - 22 C28x - Using DSP/BIOS...
Page 219 System Design Introduction This module discusses various aspects of system design. Details of the emulation and analysis block along with JTAG will be discussed and the external interface will be explored. Flash memory programming and the Code Security Module will be described. Learning Objectives Learning Objectives Learning Objectives...
Page 220 Module Topics Module Topics System Design ............................10-1 Module Topics............................10-2 Emulation and Analysis Block .......................10-3 External Interface (XINTF)........................10-7 Flash Configuration and Memory Performance ..................10-10 Flash Programming ..........................10-13 Code Security Module (CSM) ......................10-15 Lab 10: Programming the Flash......................10-19 10 - 2 C28x - System Design...
Page 221 Emulation and Analysis Block Emulation and Analysis Block JTAG Emulation System JTAG Emulation System (based on IEEE 1149.1 Standard) (based on IEEE 1149.1 Standard) System Under Test System Under Test SCAN IN SCAN IN Emulator Some Available Emulators Some Available Emulators Spectrum Digital XDS510PP+ Spectrum Digital XDS510PP+ Spectrum Digital XDS510USB...
Page 222 Emulation and Analysis Block Multiprocessor Connections Multiprocessor Connections JTAG Device JTAG Device JTAG Device JTAG Device Emulator Header Emulator Header EMU0 EMU0 EMU1 EMU1 TRST TRST TCK_RET TCK_RET Chip Emulation Analysis Block: Chip Emulation Analysis Block: Capabilities Capabilities Two hardware analysis units can be configured to provide Two hardware analysis units can be configured to provide any one of the following advanced debug features: any one of the following advanced debug features:...
Page 223 Emulation and Analysis Block Chip Emulation Analysis Block: Chip Emulation Analysis Block: Hardware Breakpoints Hardware Breakpoints Symbolic or Symbolic or numeric address numeric address Mask value for Mask value for specifying specifying address ranges address ranges Chained Chained breakpoint breakpoint selection selection Chip Emulation Analysis Block:...
Page 224 Emulation and Analysis Block Chip Emulation Analysis Block: Chip Emulation Analysis Block: Online Stack Overflow Detection Online Stack Overflow Detection Emulation analysis registers are accessible to code as well! Emulation analysis registers are accessible to code as well! Configure a watchpoint to monitor for writes near the end of Configure a watchpoint to monitor for writes near the end of the stack the stack...
Page 225: External Interface (Xintf)
External Interface (XINTF) External Interface (XINTF) TMS320F2812 XINTF Memory Map TMS320F2812 XINTF Memory Map Data Data Program Program Data Data Program Program 0x00 0000 0x00 0000 MO SARAM (1K) MO SARAM (1K) 0x00 0400 0x00 0400 M1 SARAM (1K) M1 SARAM (1K) reserved 0x00 0800 0x00 0800...
Page 226 External Interface (XINTF) F2812 XINTF Timings F2812 XINTF Timings Five external zones: 0, 1, 2, 6, 7 Five external zones: 0, 1, 2, 6, 7 Each zone has separate read and write timings Each zone has separate read and write timings XREADY signal can be used to extend ACTIVE phase XREADY signal can be used to extend ACTIVE phase XRDLEAD...
Page 227 External Interface (XINTF) XINTF Registers XINTF Registers (lab file: Xintf.c) (lab file: Xintf.c) Name Address Size (x16) Description Name Address Size (x16) Description XTIMING0 XTIMING0 0x00 0B20 0x00 0B20 XINTF Zone 0 Timing Register XINTF Zone 0 Timing Register XTIMING1 XTIMING1 0x00 0B22 0x00 0B22...
Page 228: Flash Configuration And Memory Performance
Flash Configuration and Memory Performance Flash Configuration and Memory Performance Basic Flash Operation Basic Flash Operation Flash is arranged in pages of 2048 bits Flash is arranged in pages of 2048 bits Wait states are specified for consecutive accesses Wait states are specified for consecutive accesses without a page, and random accesses across pages without a page, and random accesses across pages OTP has random access only...
Page 229 Flash Configuration and Memory Performance Other Flash Configuration Registers Other Flash Configuration Registers Address Address Name Name Description Description 0x00 0A80 0x00 0A80 FOPT FOPT Flash option register Flash option register 0x00 0A82 FPWR Flash power modes registers 0x00 0A82 FPWR Flash power modes registers 0x00 0A83...
Page 230 Flash Configuration and Memory Performance Data Access Performance Data Access Performance Assume 150 MHz SYSCLKOUT (CPU clock) Assume 150 MHz SYSCLKOUT (CPU clock) Memory bit access bit access Notes Memory bit access bit access Notes (words/cycle) (words/cycle) (words/cycle) (words/cycle) Internal RAM Internal RAM RANDWAIT = 5 RANDWAIT = 5...
Page 231: Flash Programming
Flash Programming Flash Programming Flash Programming Basics Flash Programming Basics The DSP CPU itself performs the flash programming The DSP CPU itself performs the flash programming The CPU executes Flash utility code from RAM that reads the The CPU executes Flash utility code from RAM that reads the Flash data and writes it into the Flash Flash data and writes it into the Flash We need to get the...
Page 232 Flash Programming Flash Programming Utilities Flash Programming Utilities Code Composer Studio Plug in (uses JTAG) Code Composer Studio Plug in (uses JTAG) Serial Flash loader from TI (uses SCI boot) Serial Flash loader from TI (uses SCI boot) Gang Programmers (use GPIO boot) Gang Programmers (use GPIO boot) BP Micro programmer BP Micro programmer...
Page 233: Code Security Module (Csm)
Code Security Module (CSM) Code Security Module (CSM) Code Security Module (CSM) Code Security Module (CSM) Access to the following on chip memory is Access to the following on chip memory is restricted: restricted: 0x00 8000 0x00 8000 LO SARAM (4K) LO SARAM (4K) 0x00 9000 0x00 9000...
Page 234 Code Security Module (CSM) CSM Registers CSM Registers Key Registers Key Registers – – accessible by user; EALLOW protected accessible by user; EALLOW protected Address Name Reset Value Description Address Name Reset Value Description 0x00 0AE0 KEY0 0xFFFF Low word of 128 bit Key register 0x00 0AE0 KEY0 0xFFFF...
Page 235 Code Security Module (CSM) CSM Caveats CSM Caveats Never program all the PWL’s as 0x0000 Never program all the PWL’s as 0x0000 Doing so will permanently lock the CSM Doing so will permanently lock the CSM Flash addresses 0x3F7F80 to 0x3F7FF5, Flash addresses 0x3F7F80 to 0x3F7FF5, inclusive, must be programmed to 0x0000 to inclusive, must be programmed to 0x0000 to...
Page 236 Code Security Module (CSM) CSM C Code Examples CSM C Code Examples Unlocking the CSM: Unlocking the CSM: volatile int *PWL = &CsmPwl.PSWD0; //Pointer to PWL register file volatile int *PWL = &CsmPwl.PSWD0; //Pointer to PWL register f volatile int i, tmp; volatile int i, tmp;...
Page 237: Lab 10: Programming The Flash
Lab 10: Programming the Flash Lab 10: Programming the Flash Objective The objective of this lab is to use the techniques discussed in module 10 and program the on-chip flash memory. The TMS320F2812 device has been designed for standalone operation in an embedded system.
Page 238 Lab 10: Programming the Flash Main_10.c Labcfg.cmd Lab.cdb DSP281x_Headers_BIOS.cmd User_10.cmd CodeStartBranch.asm SysCtrl.c Gpio.c DSP281x_GlobalVariableDefs.c PieCtrl_10.c DefaultIsr_9_10.c Adc.c Ev_7_8_9_10.c Filter.c Link Initialized Sections to Flash Initialized sections, such as code and constants, must contain valid values at device power-up. For a stand-alone embedded system with the F2812 device, these initialized sections must be linked to the on-chip flash memory.
Page 239 Lab 10: Programming the Flash Copying .hwi_vec Section from Flash to RAM The DSP/BIOS .hwi_vec section contains the interrupt vectors. This section must be loaded to flash (load address) but run from RAM (run address). The code that performs this copy is located in InitPieCtrl().
Page 240 Lab 10: Programming the Flash the linker has been asked to generate symbols for the load start, load end, and run start addresses. While not a requirement from a DSP hardware perspective (since the C28x DSP has a unified memory architecture). Code Composer Studio generally prefers code to be linked to program space (and data to be linked to data space).
Page 241 Lab 10: Programming the Flash 15. Open User_10.cmd and notice that the initialized sections for “passwords” and “csm_rsvd” are linked to memories named PASSWORDS and CSM_RSVD, respectively. 16. Using the DSP/BIOS configuration tool (Lab.cdb) define memory blocks for PASSWORDS and CSM_RSVD. You will need to setup the MEM Properties for each memory block with the proper base address and length.
Page 242 Lab 10: Programming the Flash Build – Lab.out 22. At this point we need to build the project, but not have CCS automatically load it since CCS cannot load code into the flash! (the flash must be programmed). On the menu bar click: Option Customize…...
Page 243 Lab 10: Programming the Flash 33. Single-Step through the bootloader code until you arrive at the beginning of the codestart section in the CodeStartBranch.asm file. (Be patient, it will take about 55 single- steps). Notice that we have placed some code in CodeStartBranch.asm to give an option to first disable the watchdog, if selected.
Page 244 Lab 10: Programming the Flash 10 - 26 C28x - System Design...
Page 245 Communications Introduction The TMS320C28x contains features that allow several methods of communication and data exchange between the C28x and other devices. Many of the most commonly used communications techniques are presented in this module. The intent of this module is not give to exhaustive design details of the communication peripherals, but rather to provide an overview of the features and capabilities.
Page 246 Module Topics Module Topics Communications............................11-1 Module Topics............................11-2 Communications Techniques .........................11-3 Serial Peripheral Interface (SPI) ......................11-4 SPI Registers .............................11-7 Serial Communications Interface (SCI) ....................11-11 Multiprocessor Wake-Up Modes.....................11-14 Multi-Channel Buffered Serial Port (McBSP) ..................11-17 Enhanced Controller Area Network (eCAN) ..................11-20 CAN Bus and Node .........................11-21 Principles of Operation........................11-22 Message Format and Block Diagram....................11-23 11 - 2...
Page 247: Communications
Communications Techniques Communications Techniques Several methods of implementing a TMS320C28x communications system are possible. The method selected for a particular design should reflect the method that meets the required data rate at the lowest cost. Various categories of interface are available and are summarized in the learning objective slide.
Page 248: Serial Peripheral Interface (Spi)
Serial Peripheral Interface (SPI) Serial Peripheral Interface (SPI) The SPI module is a synchronous serial I/O port that shifts a serial bit stream of variable length and data rate between the C28x and other peripheral devices. During data transfers, one SPI device must be configured as the transfer MASTER, and all other devices configured as SLAVES.
Page 249: Spi Block Diagram
Serial Peripheral Interface (SPI) SPI Block Diagram C28x - SPI Master Mode Shown SPISIMO RX FIFO_0 RX FIFO_15 SPIRXBUF.15-0 SPISOMI SPIDAT.15-0 SPITXBUF.15-0 TX FIFO_0 TX FIFO_15 clock clock baud LSPCLK SPICLK polarity phase rate SPI Transmit / Receive Sequence 1. Slave writes data to be sent to its shift register (SPIDAT) 2.
Page 250 Serial Peripheral Interface (SPI) Since data is shifted out of the SPIDAT register MSB first, transmission characters of less than 16 bits must be left-justified by the CPU software prior to be written to SPIDAT. Received data is shifted into SPIDAT from the left, MSB first. However, the entire sixteen bits of SPIDAT is copied into SPIBUF after the character transmission is complete such that received characters of less than 16 bits will be right-justified in SPIBUF.
Page 251: Spi Registers
Serial Peripheral Interface (SPI) SPI Registers SPI-A Configuration Control Register SPICCR @ 0x007040 15-8 reserved reserved SPI CHAR.3-0 character length = number + 1 e.g. 0000b ⇒ length = 1 1111b ⇒ length = 16 CLOCK POLARITY 0 = rising edge data transfer 1 = falling edge data transfer SPI SW RESET 0 = SPI flags reset...
Page 252 Serial Peripheral Interface (SPI) SPI-A Baud Rate Register SPIBRR @ 0x007044 Need to set this only when in master mode! 15-7 reserved SPI BIT RATE LSPCLK SPIBRR = 3 to 127 (SPIBRR + 1) SPICLK signal = LSPCLK SPIBRR = 0, 1, or 2 Baud Rate Determination: The Master specifies the communication baud rate using its baud rate register (SPIBRR.6-0): •...
Page 253 Serial Peripheral Interface (SPI) SPI-A Status Register SPISTS @ 0x007042 15-8 reserved reserved TX BUF FULL (read only) • Set to 1 when char written to SPITXBUF • Cleared when char in SPIDAT SPI INT FLAG (read only) • Set to 1 when transfer completed •...
Page 254 Serial Peripheral Interface (SPI) SPI-A FIFO Receive Register SPIFFRX @ 0x00704B RX FIFO Status (read-only) RX FIFO RX FIFO 00000 RX FIFO empty Overflow Overflow RX FIFO Reset 00001 RX FIFO has 1 word Flag Flag (read-only) Clear 0 = reset (pointer to 0) 00010 RX FIFO has 2 words 0 = no overflow...
Page 255: Serial Communications Interface (Sci)
Serial Communications Interface (SCI) Serial Communications Interface (SCI) The SCI module is a serial I/O port that permits Asynchronous communication between the C28x and other peripheral devices. The SCI transmit and receive registers are both double-buffered to prevent data collisions and allow for efficient CPU usage. In addition, the C28x SCI is a full duplex interface which provides for simultaneous data transmit and receive.
Page 256 Serial Communications Interface (SCI) SCI-A Programmable Data Format NRZ (non-return to zero) format Addr/ Parity Stop 1 Stop 2 Start LSB Data This bit present only in Address-bit mode Communications Control Register (SCICCR) – 0x007050 STOP EVEN/ODD PARITY LOOP BACK ADDR/IDLE CHAR2 CHAR1...
Page 257 Serial Communications Interface (SCI) Asynchronous Communication Format Start bit valid if 4 consecutive SCICLK periods of zero bits after falling edge • • Majority vote taken on 4th, 5th, and 6th SCICLK cycles Majority Vote SCICLK (Internal) SCIRXD LSB of Data Start Bit Falling Edge Detected Note: 8 SCICLK periods per data bit...
Page 258: Multiprocessor Wake-Up Modes
Serial Communications Interface (SCI) Baud Rate Determination: The values in the baud-select registers (SCIHBAUD and SCILBAUD) concatenate to form a 16 bit number that specifies the baud rate for the SCI. • For BRR = 1 to 65535: CLKOUT SCI Baud Rate = bits/sec ×...
Page 259 Serial Communications Interface (SCI) Idle-Line Wake-Up Mode Idle time separates blocks of frames Receiver wakes up when SCIRXD high for 10 or more bit periods Two transmit address methods deliberate software delay of 10 or more bits set TXWAKE bit to automatically leave exactly 11 idle bits Idle periods of less than...
Page 260 Serial Communications Interface (SCI) The SCI interrupt logic generates interrupt flags when it receives or transmits a complete character as determined by the SCI character length. This provides a convenient and efficient way of timing and controlling the operation of the SCI transmitter and receiver. The interrupt flag for the transmitter is TXRDY (SCICTL2.7), and for the receiver RXRDY (SCIRXST.6).
Page 261: Multi-Channel Buffered Serial Port (Mcbsp)
Multi-Channel Buffered Serial Port (McBSP) Multi-Channel Buffered Serial Port (McBSP) McBSP Block Diagram TX FIFO_15 TX FIFO_15 CLKX TX FIFO_0 TX FIFO_0 DXR2 TX Buffer DXR1 TX Buffer XSR2 XSR1 RSR2 RSR1 RBR2 Register RBR1 Register CLKR DRR2 RX Buffer DRR1 RX Buffer RX FIFO_15 RX FIFO_15...
Page 262 Multi-Channel Buffered Serial Port (McBSP) Definition: Word and Frame w0 w1 w2 w3 w4 w5 w6 w7 w6 w7 Frame Word “Frame” - contains one or multiple words Number of words per frame: 1-128 Multi-Channel Selection Ch0-0 Multi-channel Frame TDM Bit Stream Ch0-1 Transmit Ch31...
Page 263 Multi-Channel Buffered Serial Port (McBSP) McBSP Summary Direct Interface to codecs and other serial devices Full-duplex communication Independent clocking and framing for transmit and receive Internal or external clock and frame sync Data size of 8, 12, 16, 20, 24, or 32 bits 16 level 32-bit FIFO for transmit data 16 level 32-bit FIFO for receive data TDM mode - up to 128 channels...
Page 264: Enhanced Controller Area Network (Ecan)
Enhanced Controller Area Network (eCAN) Enhanced Controller Area Network (eCAN) Controller Area Network (CAN) A Multi-Master Serial Bus System CAN 2.0B Standard High speed (up to 1 Mbps) Add a node without disturbing the bus (number of nodes not limited by protocol) Less wires (lower cost, less maintenance, and more reliable) Redundant error checking (high reliability) No node addressing (message identifiers)
Page 265: Can Bus And Node
Enhanced Controller Area Network (eCAN) CAN Bus and Node CAN Bus Two wire differential bus (usually twisted pair) Max. bus length depend on transmission rate 40 meters @ 1 Mbps NODE C NODE B NODE A CAN_H 120Ω 120Ω CAN_L The DSP communicates to the CAN Bus using a transceiver.
Page 266: Principles Of Operation
Enhanced Controller Area Network (eCAN) Principles of Operation Principles of Operation Data messages transmitted are identifier based, not address based Content of message is labeled by an identifier that is unique throughout the network (e.g. rpm, temperature, position, pressure, etc.) All nodes on network receive the message and each performs an acceptance test on the identifier If message is relevant, it is processed (received);...
Page 267: Message Format And Block Diagram
Enhanced Controller Area Network (eCAN) Message Format and Block Diagram CAN Message Format Data is transmitted and received using Message Frames 8 byte data payload per message Standard and Extended identifier formats Standard Frame: 11 bit Identifier (CAN v2.0A) Standard Frame: 11 bit Identifier (CAN v2.0A) Control Arbitration...
Page 268 Enhanced Controller Area Network (eCAN) The CAN controller module contains 32 mailboxes for objects of 0 to 8-byte data lengths: • configurable transmit/receive mailboxes • configurable with standard or extended indentifier The CAN module mailboxes are divided into several parts: •...
Page 269: Development Support
Development Support Introduction This module contains various references to support the development process. Learning Objectives Learning Objectives Learning Objectives Signal Processing Libraries Signal Processing Libraries Additional Resources Additional Resources Internet Internet Product Information Center Product Information Center C28x - Development Support 12 - 1...
Page 270 Module Topics Module Topics Development Support ..........................12-1 Module Topics............................12-2 TI Support Resources..........................12-3 12 - 2 C28x - Development Support...
Page 271 TI Support Resources TI Support Resources C28x Signal Processing Libraries C28x Signal Processing Libraries Signal Processing Libraries Literature # Signal Processing Libraries Literature # ACI3 3: Simulated Indirect FOC of ACI Motor SPRC077 ACI3 3: Simulated Indirect FOC of ACI Motor SPRC077 ACI3 4: Real Direct FOC of ACI Motor ACI3 4: Real Direct FOC of ACI Motor...
Page 272 TI Support Resources European Product Information Center (EPIC) European Product Information Center (EPIC) Web: http://www-k.ext.ti.com/sc/technical_support/pic/euro.htm Phone: Language Number Belgium (English) +32 (0) 27 45 55 32 France +33 (0) 1 30 70 11 64 Germany +49 (0) 8161 80 33 11 Israel (English) 1800 949 0107 (free phone) Italy...
Page 273 Appendix A – eZdsp™ F2812 C28x - Appendix A - eZdsp F2812 A - 1...
Page 274 Appendix Module Topics Appendix ..............................A-1 Module Topics............................A-2  eZdsp F2812 ............................A-3 eZdsp F2812 Connector / Header and Pin Diagram ................A-3 P2 – Expansion Interface........................A-4 P4 / P8 / P7 – I/O Interface.........................A-5 P5 / P9 – Analog Interface........................A-7 eZdsp™...
Page 275: Ezdsp F2812
Appendix eZdsp F2812 eZdsp F2812 Connector / Header and Pin Diagram C28x - Appendix A - eZdsp F2812 A - 3...
Page 276: P2 - Expansion Interface
Appendix P2 – Expansion Interface A - 4 C28x - Appendix A - eZdsp F2812...
Page 277: P4 / P8 / P7 - I/O Interface
Appendix P4 / P8 / P7 – I/O Interface C28x - Appendix A - eZdsp F2812 A - 5...
Page 278 Appendix A - 6 C28x - Appendix A - eZdsp F2812...
Page 279: P5 / P9 - Analog Interface
Appendix P5 / P9 – Analog Interface C28x - Appendix A - eZdsp F2812 A - 7...
Page 280: Ezdsp™ F2812 Jumper Diagram
Appendix eZdsp™ F2812 Jumper Diagram JP1 – XMP/MCn Select JP2 – Flash Programming Voltage Select A - 8 C28x - Appendix A - eZdsp F2812...
Page 281: Jp7 / Jp8 / Jp11 / Jp12 - Boot Mode Select
Appendix JP7 / JP8 / JP11 / JP12 – Boot Mode Select JP9 – PLL Disable DS1 / DS2 - LEDs C28x - Appendix A - eZdsp F2812 A - 9...
Page 282: Tp1 / Tp2 - Test Points
Appendix TP1 / TP2 – Test Points A - 10 C28x - Appendix A - eZdsp F2812...
Page 283 Appendix B – Addressing Modes Introduction Appendix B will describe the data addressing modes on the C28x. Immediate addressing allows for constant expressions which are especially useful in the initialization process. Indirect addressing uses auxiliary registers as pointers for accessing organized data in arrays. Direct addressing is used to access general purpose memory.
Page 284 Module Topics Module Topics Appendix B – Addressing Modes ......................B-1 Module Topics............................B-2 Labels, Mnemonics and Assembly Directives ..................B-3 Addressing Modes........................... B-4 Instruction Formats ..........................B-5 Register Addressing ..........................B-6 Immediate Addressing..........................B-7 Direct Addressing ........................... B-8 Indirect Addressing..........................B-10 Review..............................
Page 285 Labels, Mnemonics and Assembly Directives Labels, Mnemonics and Assembly Directives Labels and Mnemonics Labels and Mnemonics .ref start .ref start Labels Labels .sect .sect “vectors” “vectors” Optional for all assembly Optional for all assembly ;make reset vector address 'start' ;make reset vector address 'start' instructions and most instructions and most reset:...
Page 286: Addressing Modes
Addressing Modes Addressing Modes Addressing Modes Addressing Modes Mode Mode Symbol Purpose Symbol Purpose Register Register Operate between Registers Operate between Registers (register) (register) Immediate Constants and Initialization Immediate Constants and Initialization (constant) (constant) Direct General purpose access to data Direct General purpose access to data...
Page 287: Instruction Formats
Instruction Formats Instruction Formats Instruction Formats Instruction Formats INSTR Example INSTR Example INSTR INSTR INSTR REG,# ACC,#1 INSTR REG,# ACC,#1 INSTR REG, AL,@x INSTR REG, AL,@x INSTR INSTR ,REG ,REG AL,@AR0 AL,@AR0 INSTR INSTR *XAR0++,#25 *XAR0++,#25 What is a “REG”? What is a “REG”? bit Access = AR0 through AR7, AH, AL, PH, PL, T and SP bit Access = AR0 through AR7, AH, AL, PH, PL, T and SP...
Page 288: Register Addressing
Register Addressing Register Addressing Register Addressing Register Addressing bit Registers bit Registers XAR0 – XAR7 XAR0 – XAR7 bit Registers bit Registers – – Allows for efficient register to register Allows for efficient register to register operation operation bit and 32 bit Register Address modes bit and 32 bit Register Address modes...
Page 289: Immediate Addressing
Immediate Addressing Immediate Addressing Immediate Addressing – “#” Immediate Addressing – “#” one word instruction one word instruction bit OPERAND bit OPERAND OPCODE OPCODE two word instruction two word instruction OPCODE OPCODE bit OPERAND bit OPERAND Fixed value part of program memory Fixed value part of program memory instruction instruction...
Page 290: Direct Addressing
Direct Addressing Direct Addressing Direct addressing allows for access to the full 4-Meg words space in 64 word “page” groups. As such, a 16-bit Data Page register is used to extend the 6-bit local address in the instruction word. Programmers should note that poor DP management is a key source of programming errors. Paged direct addressing is fast and reliable if the above considerations are followed.
Page 291 Direct Addressing Direct Addressing – Example Direct Addressing – Example Z = X + Y Z = X + Y 00 0000 0000 0001 1111 1111 00 0000 0000 0001 1111 1111 offset Data Memory usect “samp”,3 usect “samp”,3 address data data address...
Page 292: Indirect Addressing
Indirect Addressing Indirect Addressing Indirect Addressing – “ ” Indirect Addressing – “ ” Data Memory Data Memory XAR0 XAR0 XAR1 XAR1 XAR2 XAR2 XAR3 XAR3 XAR4 XAR4 XAR5 XAR5 XAR6 XAR6 XAR7 XAR7 ARAU ARAU Auxiliary Registers ( XARn ) used to access full Auxiliary Registers ( XARn...
Page 293 Indirect Addressing Indirect Addressing – Example Indirect Addressing – Example Autoincrement Autoincrement Data Data .usect “samp”,6 .set (x + 5) ∑ XAR2 XAR2 .sect “code” MOVL XAR2,#x ACC,*XAR2++ ACC,*XAR2++ ACC,*XAR2++ ACC,*XAR2++ ACC,*XAR2++ *(0:16bit) - 16 bit label - must be in lower 64K *(0:y),AL - 2 word instruction Fast, efficient access to arrays, lists, tables, etc.
Page 294 Indirect Addressing Indirect Addressing – Example Indirect Addressing – Example Stack Relative Stack Relative Data Memory Data Memory x2 = x1 + x3 x2 = x1 + x3 0 1 2 0 0 1 2 0 0 3 2 0 0 3 2 0 0 0 5 0 ? ? ? ?
Page 295 Review Review Addressing Range Review Addressing Range Review 0x000000 0x000000 0x00003F 0x00003F Stack Stack Addressing Addressing Direct Direct Addressing Addressing Indirect Indirect DP(16+6) DP(16+6) Addressing Addressing XARn XARn 0x00FFFF 0x00FFFF 0x3FFFFF 0x3FFFFF 0xFFFFFFFF 0xFFFFFFFF Data memory can be accessed in numerous ways: •...
Page 296 Review Exercise B Exercise B: Addressing Exercise B: Addressing Given: Given DP = 4000 DP = 4000 DP = 4004 DP = 4004 DP = 4006 DP = 4006 Address/Data (hex) 100030 0025 100100 0105 100180 0100 Address/Data (hex) 100030 0025 100100 0105...
Page 297 Lab B: Addressing Lab B: Addressing Objective The objective of this lab is to practice and verify the mechanics of addressing. In this process we will expand upon the ASM file from the previous lab to include new functions. Additionally, we learn how to run and observe the operation of code using Code Composer Studio.
Page 298 Lab B: Addressing Build and Load 4. Click the “Rebuild All” button and watch the tools run in the build window. Debug as necessary. To open up more space, close any open files or windows that you do not need. 5.
Page 299 OPTIONAL Lab B-C: Array Initialization in C OPTIONAL Lab B-C: Array Initialization in C Objective The objective of this lab is to practice and verify the mechanics of initialization using C. Additionally, we learn how to run and observe the operation of C code using Code Composer Studio.
Page 300 Solutions Solutions Exercise B: Addressing Solution Exercise B: Addressing Solution Given: Given DP = 4000 DP = 4000 DP = 4004 DP = 4004 DP = 4006 DP = 4006 Address/Data (hex) 100030 0025 100100 0105 100180 0100 Address/Data (hex) 100030 0025 100100...
Page 301 Appendix C – Assembly Programming Introduction Appendix C discusses the details of programming in assembly. It shows you how to use different instructions that further utilize the advantage of the architecture data paths. It gives you the ability to analyze the instruction set and pick the best instruction for the application. Learning Objectives Learning Objectives Perform simple program control using...
Page 302 Module Topics Module Topics Appendix C – Assembly Programming ....................C-1 Module Topics............................C-2 Program Control.............................C-3 Branches .............................C-3 Program Control Instructions ......................C-4 ALU and Accumulator Operations......................C-6 Simple Math & Shift...........................C-7 Multiplier ..............................C-9 Basic Multiplier ..........................C-10 Repeat Instruction..........................C-11 MAC Instruction..........................C-12 Data Move.............................C-13 Logical Operations ..........................C-15 Byte Operations and Addressing ......................C-15 Test and Change Memory Instructions.....................C-16 Min/Max Operations.........................C-17...
Page 303: Program Control
Program Control Program Control The program control logic and program address generation logic work together to provide proper program flow. Normally, the flow of a program is sequential: the CPU executes instructions at consecutive program memory addresses. At times, a discontinuity is required; that is, a program must branch to a nonsequential address and then execute instructions sequentially at that new location.
Page 304: Program Control Instructions
Program Control Program Control Instructions Program Control - Branches Function Instruction Cycles T/F Size Short Branch 8bit,cond Fast Short Branch 8bit,EQ|NEQ|TC|NTC Fast Relative Branch B 16bit,cond Fast Branch 16bit,cond Absolute Branch 22bit Dynamic Branch *XAR7 Branch on AR BANZ 16bit,ARn-- Branch on compare 16bit,ARn,ARn,EQ|NEQ Condition Code...
Page 305 Program Control BANZ Loop Control Example Auxliary register used as loop counter Auxliary register used as loop counter Branch if Auxilary Register not zero Branch if Auxilary Register not zero Test performed on lower 16 bits of XARx only Test performed on lower 16 bits of XARx only...
Page 306: Alu And Accumulator Operations
ALU and Accumulator Operations ALU and Accumulator Operations ALU and Accumulator 16/32 data mem, Product (32) 16/32 bit registers 8/16 Imm ALU and Barrel Shifter ST0, ST1 AL (15-0) AH (31-16) AH.MSB AH.LSB AL.MSB AL.LSB One of the major components in the execution unit is the Arithmetic-Logical-Unit (ALU). To support the traditional Digital Signal Processing (DSP) operation, the ALU also has the zero cycle barrel shifter and the Accumulator.
Page 307: Simple Math & Shift
ALU and Accumulator Operations Simple Math & Shift Accumulator - Basic Math Instructions xxx = instruction: MOV, ADD, SUB, ... Ax, #16b ;word Ax = AH, or AL xxxB Ax, #8b ;byte Assembler will automatically convert to 1 xxxL ACC, #32b ;long word instruction.
Page 308 ALU and Accumulator Operations 32 Bit Shift Operations [ACC] 31 ……… 0 Examples: Logical Shift Left – Long: LSLL LSLL ACC, T LSRL ACC, T 31 ……… 0 ASRL ACC, T Note: T(4:0) are used; Logical Shift Right – Long: LSRL other bits are ignored 31 ………...
Page 309: Multiplier
Multiplier Multiplier Multiply Unit Data Mem XT Register or Register T Register 32x32 Multiply Unit Prog Mem (16) 16x16 Immed (8,16) P Register (32) Shift (PM) ACC (32) Digital signal processors require many multiply and add math intensive operations. The single cycle multiplier is the second major component in the execution unit.
Page 310: Basic Multiplier
Multiplier Basic Multiplier Multiplier Instructions Instruction Execution Purpose Get first operand T,loc16 = loc16 ACC,T,loc16 ACC = T*loc16 For single or first product = T*loc16 For n product P,T,loc16 Using 8-bit unsigned const MPYB ACC,T,#8bu ACC = T*8bu Using 8-bit unsigned const MPYB P,T,#8bu = T*8bu...
Page 311: Repeat Instruction
Multiplier 32x32 Long Multiplication Integer long multiplication u(long) = u(long) * u(long) Fraction long multiplication: (long) = (long) * (long) (long) 64 = (long) 32 * (long) 32 Accumulator P-register P = u(XT)*u(loc32) IMPYAL P,XT,loc32 ACC = (XT)*(loc32) QMPYAL ACC,XT,loc32 ACC += P;...
Page 312: Mac Instruction
Multiplier Single repeat instruction (RPT) is used to reduce code size and speed up many operations in the DSP application. Some of the most popular operations that use the RPT instruction to perform multiple taps digital filters or perform block of data transfer. MAC Instruction Sum-of-Products: RPT / MAC usect...
Page 313: Data Move
Data Move Data Move Data Move Instructions DATA ↔ DATA (4G ↔ 64K) DATA ↔ PGM (4G ↔ 4M) loc16, *(0:16bit) PREAD loc16 ,*XAR7 *(0:16bit), loc16 PWRITE *XAR7, loc16 32-bit address memory 16-bit address concatenated pointer with a 22-bit location program memory address with 16 leading zeros .sect...
Page 314 Data Move place the contents of A into the accumulator. Once the Ax content is tested, by using the CMP instruction, the conditional move can be executed. If the specified condition being tested is true, then the location pointed to by the “loc16” address- ing mode or the 8–bit zero extended constant will be loaded with the contents of the specified AX register (AH or AL): if (COND == true) [loc16] = AX or 0:8bit;...
Page 315: Logical Operations
Logical Operations Logical Operations Byte Operations and Addressing Byte Operations MOVB AX.LSB,loc16 0000 0000 Byte MOVB AX.MSB,loc16 Byte No change No change Byte MOVB loc16, AX.LSB loc16 No change Byte MOVB loc16, AX.MSB loc16 Byte = 1. Low byte for register addressing 2.
Page 316: Test And Change Memory Instructions
Logical Operations Test and Change Memory Instructions The compare (CMPx) and test (Txxx) instructions allow the ability to test values in memory. The results of these operations can then trigger subsequent conditional branches. The CMPx instruc- tion allows comparison of memory with respect to a specified constant value, while the Txxx in- structions allow any single bit to be extracted to the test control (TC) field of status register 0.
Page 317 Logical Operations Min/Max Operations MIN/MAX Operations Instruction Execution ACC,loc16 if ACC < loc16, ACC = loc16 if ACC >= loc16, do nothing ACC,loc16 if ACC > loc16, ACC = loc16 if ACC <= loc16, do nothing MAXL ACC,loc32 if ACC < loc32, ACC = loc32 if ACC >= loc32, do nothing MINL ACC,loc32...
Page 318: Read Modify Write Operations
Read Modify Write Operations Read Modify Write Operations The accumulator (ACC) is the main working register for the C28x. It is the destination of all ALU operations except those, which operate directly on memory or registers. The accumulator supports single-cycle move, add, subtract and compare operations from 32-bit-wide data memory. It can also accept the 32-bit result of a multiplication operation.
Page 319 Read Modify Write Operations Read-Modify-Write Examples update by 1 update with a mem update with a constant VarA += 1 VarA += 100 VarA += VarB SETC INTM SETC INTM SETC INTM AL, @VarB AL, @VarA AL, @VarA AL, @VarA AL, #100 @VarA, AL @VarA, AL...
Page 320: Lab C: Assembly Programming
Lab C: Assembly Programming Lab C: Assembly Programming Objective The objective of this lab is to practice and verify the mechanics of performing assembly language programming arithmetic on the TMS320C28x. In this process we will expand upon the .asm file from the previous lab to include new functions.
Page 321 Lab C: Assembly Programming Build and Load 5. Click the “Rebuild All” button and watch the tools run in the build window. Debug as necessary. To open up more space, close any open files or windows that you do not need.
Page 322: Optional Lab C-C: Sum-Of-Products In C
OPTIONAL Lab C-C: Sum-of-Products in C OPTIONAL Lab C-C: Sum-of-Products in C Objective The objective of this lab is to practice and verify the mechanics of performing C programming arithmetic on the TMS320C28x. The objective will be to add the code necessary to obtain the sum of the products of the n-th values from each array.
Page 323 Appendix D – C Programming Introduction The C28x architecture, hardware, and compiler has been designed to efficiently support C code programming. Appendix D will focus on how to program in C for an embedded system. Issues related to programming in C and how C behaves in the C28x environment will be discussed. Also, the C compiler optimization features will be explained.
Page 324 Module Topics Module Topics Appendix D – C Programming.........................D-1 Module Topics............................D-2 Linking Boot code from RTS2800.lib ......................D-3 Set up the Stack ............................D-4 C28x Data Types.............................D-5 Accessing Interrupts / Status Register.....................D-6 Using Embedded Assembly ........................D-7 Using Pragma ............................D-8 Optimization Levels ..........................D-9 Volatile Usage ..........................D-11 Compiler Advanced Options ......................D-12 Optimization Tips Summary......................D-13...
Page 325: Linking Boot Code From Rts2800.Lib
Linking Boot code from RTS2800.lib Linking Boot code from RTS2800.lib Invoked With ” Invoked With ” Boot.ASM “ Boot.ASM “ Reset : PC < *0x3F FFC0 Reset : PC < *0x3F FFC0 vectors. vectors. .ref _c_int00 .ref _c_int00 Reset: Reset: .long _c_int00 .long...
Page 326: Set Up The Stack
Set up the Stack Set up the Stack The Stack The Stack Data Memory Data Memory The C/C++ compiler uses a The C/C++ compiler uses a stack to: stack to: Allocate local variables Allocate local variables 0x400 0x400 Caller’s Caller’s Pass arguments to Pass arguments to (reset)
Page 327 C28x Data Types C28x Data Types C28x C Language Data Types C28x C Language Data Types Type Value Range Type Value Range char char Usually 0 .. 255, but can hold 16 bits Usually 0 .. 255, but can hold 16 bits 32K ..
Page 328: Accessing Interrupts / Status Register
Accessing Interrupts / Status Register Accessing Interrupts / Status Register Accessing Interrupts / Status Register Accessing Interrupts / Status Register Initialize via C : Initialize via C : extern extern cregister cregister volatile unsigned volatile unsigned IFR; IFR; extern extern cregister cregister volatile unsigned...
Page 329: Using Embedded Assembly
Using Embedded Assembly Using Embedded Assembly Embedding Assembly in C Embedding Assembly in C Allows direct access to assembly language from C Allows direct access to assembly language from C Useful for operating on components not used by C, ex: Useful for operating on components not used by C, ex: asm ( “...
Page 330: Using Pragma
Using Pragma Using Pragma Pragma is a preprocessor directive that provides directions to the compiler about how to treat a particular statement. The following example shows how the DATA_SECTION pragma is used to put a specific buffer into a different section of RAM than other buffers. The example shows two buffers, bufferA and bufferB.
Page 331: Optimization Levels
Optimization Levels Optimization Levels Optimization Scope Optimization Scope FILE1.C FILE1.C SESE SESE LOCAL LOCAL single block single block FUNCTION FUNCTION ..across across FILE FILE SESE: Single Entry, Single Exit SESE: Single Entry, Single Exit blocks blocks across...
Page 332 Optimization Levels Optimization Performance Optimization Performance – – Performs control flow graph simplification Performs control flow graph simplification Allocates variables to registers Allocates variables to registers Performs loop rotation Performs loop rotation LOCAL LOCAL Eliminates unused code Eliminates unused code Simplifies expressions and statements Simplifies expressions and statements Expands calls to functions declared inline...
Page 333: Volatile Usage
Optimization Levels Volatile Usage Optimization Issue: “Volatile” Variables Optimization Issue: “Volatile” Variables Problem: Problem: The compiler does not know that this pointer may refer to a The compiler does not know that this pointer may refer to a hardware register that may change outside the scope of the C pro hardware register that may change outside the scope of the C pro gram.
Page 334: Compiler Advanced Options
Optimization Levels Compiler Advanced Options To get to these options, go to Project Build Options in Code Composer Studio. In the category, pick Advanced. The first thing to notice under advanced options is the Auto Inlining Threshold. - Used with –o3 option - Functions >...
Page 335: Optimization Tips Summary
Optimization Levels Optimization Tips Summary Summary: Optimization Tips Summary: Optimization Tips Within C functions : Within C functions : Use const with variables for parameter constants Use const with variables for parameter constants Minimize mixing signed & unsigned ops Minimize mixing signed & unsigned ops : SXM changes : SXM changes Keep frames <= 64 (locals + parameters + PC)
Page 336: Lab D: C Optimization
Lab D: C Optimization Lab D: C Optimization Objective The objective of this lab is to practice and verify the mechanics of optimizing C programs. Using Code Composer Studio profile capabilities, different routines in a project will be benchmarked. This will allow you to analyze the performance of different functions. This lab will highlight the profiler and the clock tools in CCS.
Page 337 Lab D: C Optimization 6. Set up the profile session by selecting Profiler Start New Session. Enter a session name of your choice (i.e. LabD). 7. In the profiler window, hover the mouse over the icons on the left region of the window and select the icon for Profile All Functions.
Page 338 Lab D: C Optimization 17. Double Click on the clock to reset it. Run to the last breakpoint. Record the number of cycles the assembly code ran. 18. How does assembly, C code, and oprimized C code compare on the C28x? C Code Optimized C Code (-o3) Assembly Code...
Page 339 OPTIONAL Lab D2: C Callable Assembly OPTIONAL Lab D2: C Callable Assembly Objective The objective of this lab is to practice and verify the mechanics of implementing a C callable assembly programming. In this lab, a C file will be used to call the sum-of-products (from the previous Appendix LabC exercise) by the “main”...
Page 340 OPTIONAL Lab D2: C Callable Assembly Verify C Sum of Products Routine 6. Debug using both source and assembly (by right clicking on the window and select Mixed Mode or using View → Mixed Source/ASM). 7. Open a memory window to view result and data. 8.
Page 341 OPTIONAL Lab D2: C Callable Assembly Now we need to return the result. To return a value to the calling routine you will need to place your 32-bit value in the ACC. What register is the result currently in? Adjust your code, if necessary.
Page 342 Solutions Solutions Lab D Solutions Lab D Solutions C Code Optimized Assembly C Code Optimized Assembly C Code Code C Code Code Code Size Code Size Cycles Cycles D- 20 C28x – C Programming...

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