Cache Configuration Register Fields (Ccfg) - Texas Instruments TMS320C6201 Reference Manual

4.5 L2 Description
Figure 4–12. Cache Configuration Register Fields (CCFG)
31 30
P
RW,+0
Table 4–6. Cache Configuration Register Field Description
Field
L2MODE
ID
IP
P
The L2 is accessible from both the L1P and the L1D. On a cache miss from
the L1P or L1D, the request is first sent to the L2 to be serviced. How the L2
services the request depends on the selected operation mode of the L2.
Table 4–6 shows the supported operation modes for the L2. Figure 4–13 illus-
trates the division of the L2 memory space according to the L2 Mode.
Writing to the L2MODE field of the cache configuration register (CCFG) sets
the L2 mode. Figure 4–12 shows the format for the CCFG register. Table 4–6
describes the operation of this register.
10
rsvd
R,+x
Description
L2 Operation Mode
L2MODE = 000b: 64K bytes SRAM
L2MODE = 001b: 16K bytes 1-way cache / 48 Kbytes mapped RAM
L2MODE = 010b: 32K bytes 2-way cache / 32 Kbytes mapped RAM
L2MODE = 011b: 48K bytes 3-way cache / 16 Kbytes mapped RAM
L2MODE = 111b: 64K bytes 4-way cache
L2MODE = other: Reserved
Invalidate L1D
ID = 0: Normal L1D operation
ID = 1: All L1D lines invalidated
Invalidate LIP
IP = 0: Normal L1P operation
IP = 1: All L1P lines invalidated
L2 Requestor Priority
P = 0: CPU accesses prioritized over enhanced DMA accesses
P = 1: Enhanced DMA accesses prioritized over CPU accesses
TMS320C6211/C6711 Two-Level Internal Memory
9 8 7
IP ID
W,+0
W,+0
L2 Description
3 2
rsvd L2MODE
R,+0 0000 RW,+000
0
4-13