9.6 Asynchronous Interface; Emif Asynchronous Interface Pins - Texas Instruments TMS320C6201 Reference Manual

9.6 Asynchronous Interface

Table 9–18. EMIF Asynchronous Interface Pins
The asynchronous interface offers configurable memory cycle types to interface
to a variety of memory and peripheral types, including SRAM, EPROM, and flash
memory, as well as FPGA and ASIC designs.
Table 9–18 lists the asynchronous interface pins.
Figure 9–36 shows an interface to standard SRAM, and Figure 9–38,
Figure 9–39, and Figure 9–40 show interfaces to 8-, 16-, and 32-bit ROM for
the 'C6201/C6202/C6701 and for the 'C6211/C6711 in little-endian mode. Al-
though ROM can be interfaced at any of the CE spaces, it is often used at CE1
because that space can be configured for widths of less than 32 bits on the
'C6201/C6202/C6701. The 'C6211/C6711 allows 8/16 bit asynchronous mode
in any CE space. Figure 9–37 shows the 'C6211/C6711 interface to 16-bit
asynchronous SRAM in big endian mode. The only difference is that ED[31:16]
pins are used instead of ED[15:0]. The asynchronous interface signals on the
'C6211/C6711 are similar to the 'C6201, except that the signals have been
combined with the SDRAM and SBSRAM memory interface. It has also been
enhanced to allow for longer read hold and write hold times, and the 8- and
16-bit interface modes have been extended to include writable asynchronous
memories, instead of ROM devices. A programmable turnaround time (TA)
also allows the user to control the number of cycles between a read and a write
to avoid bus contention.
EMIF
Signal Function
AOE Output enable. Active (low) during the entire period of a read access.
AWE Write enable. Active (low) during a write transfer strobe period.
ARE Read enable. Active (low) during a read transfer strobe period.
ARDY Ready. Input used to insert wait states into the memory cycle.
Asynchronous Interface
External Memory Interface 9-49