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Synchronization: Triggering DMA Transfers
Figure 5–7. Synchronization Flags
EXT_INTx (active low)
EXT_INTx (active high)
DMA frame In progress
DMA sync event
5-20
Figure 5–7 shows the scenario to produce the desired synchronizing event.
The figure illustrates both active-high and active-low operation, but the
following explanation pertains to active-low operation.
1) The transition of EXT_INTx from high-to-low while a burst is not in prog-
ress triggers a synchronizing event.
2) The synchronizing event triggers a frame transfer, which gates off the
DMA sync event. During the sync event, transitions on EXT_INTx are ig-
nored.
3) Same as 1
4) Same as 2
5) If EXT_INTx is still active after the burst, then the high-to-low transition on
the internal frame-in-progress signal causes a DMA sync event.
6) The new DMA sync event triggers another burst.
2
Read burst
1
The new synchronization modes are available to better interface to an external
FIFO that is serving as a data buffer. Since a synchronization event is often
triggered off of a flag indicating the amount of data currently inside the FIFO,
there is a high likelihood that a race-condition could occur. If the DMA were to
read from the FIFO (clearing the flag that generated the synchronization
event), and a new element were written to the FIFO immediately after, then the
flag could be reset and a new frame would be synchronized to start
immediately following the current burst. By setting the DMA to ignore events
during a current burst, this situation is avoided.
4
6
3
5
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