Sbsram Reads 9; Sbsram Four-Word Read; Emif Sbsram Pins - Texas Instruments TMS320C6201 Reference Manual

Table 9–17. EMIF SBSRAM Pins
9.5.1 SBSRAM Reads
Figure 9–32. SBSRAM Four-Word Read
Clock †
CEx
BE[3:0]
EA[21:2]
ED[31:0]
SSADS
SSOE
SSWE
† Clock=SSCLK for 'C6201/C6701.
Clock=CLKOUT2 for 'C6202.
EMIF Signal
SSADS
SSOE
SSWE
SSCLK/CLKOUT2/ECLKOUT
SBSRAMs are latent by their architecture, meaning that read data follows
address and control information. Consequently, the EMIF inserts cycles between
read and write commands to ensure that no conflict exists on the ED[31:0] bus.
The EMIF keeps this turnaround penalty to a minimum. The initial 2-cycle penalty
occurs when the direction changes on the bus. In general, the first access of a
burst sequence incurs a 2-cycle start-up penalty.
Figure 9–32 shows a four-word read of an SBSRAM for the 'C6201/C6202/
C6701. Every access strobes a new address into the SBSRAM, indicated by
the SSADS strobe low. The first access requires an initial start-up penalty of
two cycles; thereafter, all accesses occur in a single SSCLK cycle.
BE1
A1
SBSRAM Signal
ADSC
OE
WE
CLK
Read Read Read
D1
latched
BE2 BE3 BE4
A2 A3 A4
Q1 Q2
External Memory Interface
SBSRAM Interface
SBSRAM Function
Address strobe
Output enable
Write enable
SBSRAM clock
Read D3 D4
D2 latched latched
latched
Q3 Q4
9-45