Figure 7–8. HPI Write Timing (HAS Not Used, Tied High)
HAS
HCNTL[1:0]
HBE[1:0]
HR/W
HHWIL
HSTROBE
HCS
HD[15:0]
HRDY
Figure 7–9. HPI Write Timing (HAS Used)
HAS
HBE[1:0]
HCNTL[1:0]
HR/W
HHWIL
HSTROBE
HD[15:0]
HRDY
1st halfword
1st halfword
HPI Signal Descriptions
2nd halfword
2nd halfword
Host-Port Interface
7-15