L1D Flush Base Address Register Fields (L1Dfbar); L1D Flush Word Count Register Fields (L1Dfwc) - Texas Instruments TMS320C6201 Reference Manual

L1D Description
Figure 4–10. L1D Flush Base Address Register Fields (L1DFBAR)
31
Figure 4–11. L1D Flush Word Count Register Fields (L1DFWC)
31
4-12
There are two methods for user-controlled invalidation of data in the L1D. Writ-
ing a 1 to the ID bit of the cache configuration register (CCFG) invalidates all
the cache tags in the L1D tag RAM. This is a write-only bit, a read of this bit
returns a 0. Any CPU access to the L1D while invalidation is being processed
stalls until the invalidation has completed and the CPU request has been
fetched.
The second method for invalidating the L1D requires the L1DFBAR and
L1DFWC registers. This is useful for invalidating a block of data in the L1D.
You must first write a word-aligned address into the L1DFBAR. This value is
used as the starting address for the invalidation. The number of words invali-
dated equals the value written into the L1DFWC register. The L1D searches
for and invalidate all lines whose external memory address falls within the
range from L1DFBAR to L1DFBAR+L1DFWC–4. The data in these lines is
sent to the L2 to be stored in the original memory location. In this way, the L2
and external memory will remain coherent with the data that is invalidated.
If L1DFBAR or L1DFWC are not aligned to the L1D line size (8 words) all lines
which contain data in the address range specified are invalidated. However
only those words that are contained in the range from L1DFBAR to
L1DFBAR+L1DFWC–4 will be saved to the L2. This block invalidation will oc-
cur in the background and not stall any pending CPU accesses. The block in-
validation begins when the L1DFWC is written, therefore you should take care
to ensure that the L1DFBAR register is set up correctly prior to writing the
L1DFWC. This is the preferred method for writing data that has been cached
in the L1D to the external memory space. Figure 4–10 and Figure 4–11 show
the format for the L1DFBAR and L1DFWC.
L1D flush base address
16
rsvd
R,+x
RW,+x
15
L1D flush word count
RW,+x
0
0