L2 Flush Register Fields (L2Flush); L2 Clean Register Fields (L2Clean); L2 Flush Base Address Register Fields (L2Fbar); L2 Flush Register Fields Description - Texas Instruments TMS320C6201 Reference Manual

L2 Description
Figure 4–16. L2 Flush Register Fields (L2FLUSH)
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Table 4–8. L2 Flush Register Fields Description
Figure 4–17. L2 Clean Register Fields (L2CLEAN)
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Table 4–9. L2 Clean Register Fields Description
Figure 4–18. L2 Flush Base Address Register Fields (L2FBAR)
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4-22
rsvd
R,+x
Field Description
F Flush L2
F = 0: Normal L2 operation
F = 1: All L2 lines flushed
rsvd
R,+x
Field Description
C Clean L2
C = 0: Normal L2 operation
C = 1: All L2 lines cleaned
It is also possible to flush and clean a range of addresses from the L2. To flush
a range of address from the L2, write the word–aligned address for the start
of the flush into the L2FBAR. The number of words to be flushed is equal to
the value written into the L2FWC register. The L2 controller then searches all
L2 cache blocks for all lines whose external memory address falls within the
range from L2FBAR to L2FBAR+L2FWC–4 and copies that data through the
EDMA to the external memory space. The L1D is snooped to ensure that the
correct data is stored in the original memory location. The L2 flush occurs in
the background and does not stall any pending CPU accesses. The flush be-
gins when the L2FWC is written, therefore you should take care to ensure that
the L2FBAR register is set up correctly prior to writing the L2FWC. Figure 4–18
shows the fields in the L2FBAR register. Figure 4–19 shows the fields in the
L2FWC register.
L2 Flush Base Address
RW,+x
1 0
F
RW,+0
1 0
C
RW,+0
0