Texas Instruments TMS320C6000 Reference Manual
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Texas Instruments TMS320C6000 Reference Manual

Texas Instruments TMS320C6000 Reference Manual

Dsp designing for jtag emulation
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TMS320C6000 DSP
Designing for JTAG Emulation
Reference Guide
Literature Number: SPRU641
July 2003

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  • Page 1 TMS320C6000 DSP Designing for JTAG Emulation Reference Guide Literature Number: SPRU641 July 2003...
  • Page 2 TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions:...
  • Page 3 JTAG 3/5 V and supports both standard 3-volt and 5-volt target system power inputs. The term JTAG as used in this document refers to Texas Instruments scan- based emulation, which is based on the IEEE 1149.1 standard.
  • Page 4 TMS320C6x Peripheral Support Library Programmer’s Reference (literature number SPRU273) describes the contents of the TMS320C6000 peripheral support library of functions and macros. It lists functions and macros both by header file and alphabetically, provides a complete description of each, and gives code examples to show how they are used.

  • Page 5: Table Of Contents

    Contents Contents Designing Your Target System’s Emulator Connector (14-Pin Header) ....Bus Protocol ..............IEEE 1149.1 Standard .
  • Page 6 Figures Figures 14-Pin Header Signals and Header Dimensions ........JTAG Emulator Cable Pod Interface .

  • Page 7: Designing Your Target System's Emulator Connector (14-Pin Header)

    JTAG 3/5 V and supports both standard 3-volt and 5-volt target system power inputs. The term JTAG as used in this document refers to Texas Instruments scan- based emulation, which is based on the IEEE 1149.1 standard.
  • Page 8 Designing Your Target System’s Emulator Connector (14-Pin Header) Table 1. 14-Pin Header Signal Descriptions † † Emulator Target Signal Description State State Test mode select Test data input Test data output Test clock. TCK is a 10.368-MHz clock source from the emulation cable pod.

  • Page 9: Bus Protocol

    Designing Your Target System’s Emulator Connector (14-Pin Header) Bus Protocol / IEEE 1149.1 Standard Bus Protocol The IEEE 1149.1 specification covers the requirements for the test access port (TAP) bus slave devices and provides certain rules, summarized as follows: The TMS/TDI inputs are sampled on the rising edge of the TCK signal of the device.

  • Page 10: Jtag Emulator Cable Pod Logic

    JTAG Emulator Cable Pod Logic JTAG Emulator Cable Pod Logic Figure 2 shows a portion of the emulator cable pod. These are the functional features of the pod: Signals TDO and TCK_RET can be parallel-terminated inside the pod if required by the application. By default, these signals are not terminated. Signal TCK is driven with a 74LVT240 device.

  • Page 11: Jtag Emulator Cable Pod Signal Timing

    These timing parameters are calculated from values specified in the standard data sheets for the emulator and cable pod and are for reference only. Texas Instruments does not test or guarantee these timings. The emulator pod uses TCK_RET as its clock source for internal synchroni- zation.

  • Page 12: Emulation Timing Calculations

    Emulation Timing Calculations Emulation Timing Calculations The following examples help you calculate emulation timings in your system. For actual target timing parameters, see the appropriate device data sheets. Assumptions: Target TMS/TDI setup to TCK high 10 ns su(TTMS) Target TDO delay from TCK low 15 ns d(TTDO) Target buffer delay, maximum...
  • Page 13 Emulation Timing Calculations Case 2: Single/multiprocessor, TMS/TDI/TCK buffered input, TDO buffered output, TMS/TDI timed from TCK_RET low. d (TMSmax su (TTMS (bufskew) pd (TCK_RET–TMS TDI) TCKfactor 20ns ) 10ns ) 1.35 ns + 78.4ns ( 12.7 MHz ) d (TTDO su (TDOmin) d (bufmax pd (TCK_RET–TDO)

  • Page 14: Connections Between The Emulator And The Target System

    Connections Between the Emulator and the Target System Connections Between the Emulator and the Target System It is extremely important to provide high-quality signals between the emulator and the JTAG target system. Depending upon the situation, you must supply the correct signal buffering, test clock inputs, and multiple processor intercon- nections to ensure proper emulator and target system operation.
  • Page 15 Connections Between the Emulator and the Target System Buffered transmission signals. In this situation, the distance between the emulation header and the processor is greater than 6 inches. Emula- tion signals TMS, TDI, TDO, and TCK_RET are buffered through the same package.

  • Page 16: Using A Target-System Clock

    Connections Between the Emulator and the Target System Using a Target-System Clock Figure 4 shows an application with the system test clock generated in the target system. In this application, the TCK signal is left unconnected. Figure 4. Target-System-Generated Test Clock Greater Than 6 Inches V CC...

  • Page 17: Configuring Multiple Processors

    Connections Between the Emulator and the Target System Configuring Multiple Processors Figure 5 shows a typical daisy-chained multiprocessor configuration, which meets the minimum requirements of the IEEE 1149.1 specification. The emu- lation signals in this example are buffered to isolate the processors from the emulator and provide adequate signal drive for the target system.

  • Page 18: Mechanical Dimensions For The 14-Pin Emulator Connector

    Mechanical Dimensions for the 14-Pin Emulator Connector Mechanical Dimensions for the 14-Pin Emulator Connector The JTAG emulator target cable consists of a 3-foot section of jacketed cable, an active cable pod, and a short section of jacketed cable that connects to the target system.
  • Page 19 Mechanical Dimensions for the 14-Pin Emulator Connector Figure 7. 14-Pin Connector Dimensions 0.20 Cable 0.66 Connector, Side View Key, Pin 6 0.100 0.87 Cable 0.100 Connector, Front View Pins 2, 4, 6, 8, 10, 12, 14 Pins 1, 3, 5, 7, 9, 11, 13 Note: All dimensions are in inches and are nominal dimensions, unless otherwise specified.

  • Page 20: Emulation Design Considerations

    Emulation Design Considerations Emulation Design Considerations This section describes the use and application of the scan path linker (SPL), which can simultaneously add all four secondary JTAG scan paths to the main scan path. It also describes the use of the emulation pins and the configuration of multiple processors.

  • Page 21: Connecting A Secondary Jtag Scan Path To An Spl

    Emulation Design Considerations Figure 8. Connecting a Secondary JTAG Scan Path to an SPL † JTAG 0 DTCK DTDO0 DTMS0 DTDI0 TRST TRST DTDO1 DTMS1 DTDI1 JTAG N DTDO2 DTMS2 DTDI2 TRST DTDO3 DTMS3 DTDI3 † Voltage translators should be used between the SPL (5V) and the C6000 (3V). The TRST signal from the main scan path drives all devices, even those on the secondary scan paths of the SPL.

  • Page 22: Emulation Timing Calculations For Spl

    Emulation Design Considerations Emulation Timing Calculations for SPL The following examples help you to calculate the emulation timings in the SPL secondary scan path of your system. For actual target timing parameters, see the appropriate device data sheets. Assumptions: Target TMS/TDI setup to TCK high 10 ns su(TTMS) Target TDO delay from TCK low...
  • Page 23 Emulation Design Considerations Case 1: Single processor, direct connection, DTMS/DTDO timed from TCK low. d DTMSmax d DTCKHmin su TTMS pd TCK–DTMS TCKfactor [ 31ns ) 2ns ) 10ns ] + 107.5ns ( 9.3 MHz ) d TTDO d DTCKLmax su DTDLmin pd TCK–DTDI TCKfactor...

  • Page 24: Using Emulation Pins

    Emulation Design Considerations Using Emulation Pins The EMU0/1 pins of TI devices are bidirectional, three-state output pins. When in an inactive state, these pins are at high impedance. When the pins are active, they function in one of the two following output modes: Signal Event The EMU0/1 pins can be configured via software to signal internal events.

  • Page 25: Emu0/1 Configuration

    Emulation Design Considerations Figure 9. EMU0/1 Configuration Target Board 1 Pullup Resistor Open Collector EMU0/1 Drivers Backplane Device Device . . . XCNT_ENABLE EMU0/1-IN Pullup Resistor EMU0/1-OUT Target Board m Pullup Resistor To Emulator EMU0 Open EMU0/1 Collector Drivers Device Device .
  • Page 26 Emulation Design Considerations  The bused EMU0/1 signals go into a PAL device, whose function is to generate a low pulse on the EMU0/1-IN signal when a low level is detected on the EMU0/1-OUT signal. This pulse must be longer than one TCK period to affect the devices, but less than 10 µs to avoid possible conflicts or retriggering, once the emulation software clears the device’s pins.

  • Page 27: Emu0/1 Configuration With Additional And Gate To Meet Timing Requirements

    Emulation Design Considerations Figure 10. EMU0/1 Configuration With Additional AND Gate to Meet Timing Requirements Target Board 1 Pullup Resistor Open Collector EMU0/1 Drivers Device Device Backplane . . . XCNT_ENABLE EMU0/1-IN Pullup Resistor EMU0/1-OUT Target Board m Pullup Resistor To Emulator EMU0 Open Circuitry required for >25-ns rising/...

  • Page 28: Performing Diagnostic Applications

    For systems that require built-in diagnostics, it is possible to connect the emulation scan path directly to a TI ACT8990 test bus controller (TBC) instead of the emulation header. The TBC is described in the Texas Instruments Advanced Logic and Bus Interface Logic Data Book (literature number SCYD001).

  • Page 29: Tbc Emulation Connections For N Jtag Scan Paths

    Emulation Design Considerations Figure 13. TBC Emulation Connections for n JTAG Scan Paths † V CC Clock TCKI JTAG0 TMS0 TMS1 EMU0 TMS2/EVNT0 EMU1 TMS3/EVNT1 TRST TMS4/EVNT2 TMS5/EVNT3 TCKO TDI0 JTAGn TDI1 EMU0 EMU1 TRST † Voltage translators should be used between the TBC (5V) and the C6000 DSP (3V). In the system design shown in Figure 13, the TBC emulation signals TCKI, TDO, TMS0, TMS2/EVNT0, TMS3/EVNT1, TMS5/EVNT3, TCKO, and TDI0 are used, and TMS1, TMS4/EVNT2, and TDI1 are not connected.
  • Page 30 Designing for JTAG Emulation SPRU641...
  • Page 31 Index Index EMU0/1 block diagram configuration 25 connecting a secondary JTAG scan path to an with additional AND gate to meet timing SPL 21 requirements 27 EMU0/1 configuration 25 without global stop 28 EMU0/1 configuration with additional AND gate emulation pins 24 to meet timing requirements 27 rising edge modification 27 EMU0/1 configuration without global stop 28...
  • Page 32 3 timing 11 protocol, bus 9 TBC emulation connections for n JTAG scan paths 29 test clock 16 timing calculations 12, 22 related documentation from Texas Instruments 3 run/stop operation 14 trademarks 4 Designing for JTAG Emulation SPRU641...

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