Sdram Read; Tms3206201/C6202/C6701 Sdram Read - Texas Instruments TMS320C6201 Reference Manual

9.4.8

SDRAM Read

9.4.8.1 TMS320C6201
Figure 9–24. TMS3206201/C6202/C6701 SDRAM Read
Clock †
CEx
BE[3:0]
EA[15:2]
ED[31:0]
SDA10
SDRAS
SDCAS
SDWE
† Clock=SDCLK for 'C6201/C6701.
Clock=CLKOUT2 for 'C6202.
/ /
C6202 C6701 SDRAM Read
During an SDRAM read, the selected bank is activated with the row address
during the ACTV command. Figure 9–24 shows the timing for the
'C6201/C6202/C6701 issuing three read commands performed at three different
column addresses. The EMIF uses a CAS latency of three and a burst length of
one. The three-cycle latency causes data to appear three cycles after the cor-
responding column address. Following the final read command of the
'C6201/C6202/C6701, an idle cycle is inserted to meet timing requirements. If
required, the bank is then deactivated with a DCAB command and the EMIF can
begin a new page access. If no new access is pending or an access is pending
to the same page, the DCAB command is not performed until the page informa-
tion becomes valid. The values on EA[15:13] during column accesses and execu-
tion of the DCAB command are the values latched during the ACTV command.
Read Read
BE1
CA1 CA2
CAS latency = 3
D1
Read
latched
BE2 BE3
CA3
D1
External Memory Interface
SDRAM Interface
D2 D3
latched latched
D2 D3
9-37