Xbhc Register Description - Texas Instruments TMS320C6201 Reference Manual

Figure 8–18. Expansion Bus Host Port Interface Control (XBHC) Register
31
15
Reserved
R,+0000 0000 00
Note: R = Read, W = Write, +0 =Reset value
Table 8–15. XBHC Register Description
The START bit field in the XBHC register is not cleared to zero after a transfer
is completed. Writing '00' to the the START field, when a transfer in progress
is stalled by XRDY high, aborts the transfer. When a transfer is aborted the
XBIMA and XBEA registers and the XFRCT transfer counter reflect the state
of the aborted transfer. Using this state information, the transfer can be re-
started. Writing other values than '00' to the START field is not recommended.
RW,+0000 0000 0000 0000
6 5
INTSRC
RW, +0
Field Description
DSPINT The external master to DSP interrupt (used to wake up the DSP
from reset) is cleared when this bit is set.
START[1:0] Start bus master transaction
Start = 01: starts a write burst transaction from address
Start = 10: starts a read burst transaction from address
Writing '00' to the the START field, while an active transfer is
stalled by XRDY high, aborts the transfer. When a transfer is
aborted the expansion bus registers reflect the state of the
aborted transfer. Using this state information, you can restart
the transfer.
INTSRC The expansion bus host port interrupt can be caused either by
DSPINT bit or by XFRCT counter. The INTSRC selects
interrupt source between DSPINT and XFRCT counter.
INTSRC=0: interrupt source is DSPINT bit
INTSRC=1: interrupt is generated at the completion of the
master transfer initiated by writing to the START bit-field.
XFRCT Transfer counter controls the number of elements transferred
between the expansion bus and an external slave when the
CPU is mastering the bus ( range of up to 64k).
Expansion Bus Host Port Operation
XFRCT
4 3
START Reserved
RW, +00
pointed by XBIMA to address pointed by XBEA
pointed by XBEA to address pointed by XBIMA
2 1
DSPINT
RW, +0
Expansion Bus
16
0
Reserved
8-25