Dma Channel Source Address Register; Dma Channel Destination Address Register; Address Generation - Texas Instruments TMS320C6201 Reference Manual

Address Generation

5.7 Address Generation
Figure 5–8. DMA Channel Source Address Register
31
Figure 5–9. DMA Channel Destination Address Register
31
5.7.1 Basic Address Adjustment
5-22
For each channel, the DMA controller performs address computation for each
read transfer and write transfer. The DMA controller allows creation of a variety
of data structures. For example, the DMA controller can traverse an array incre-
menting through every nth element. Also, you can program it to effectively treat
the various elements in a frame as coming from separate sources and group
each source's data together.
The DMA channel source address and destination address registers (shown
in Figure 5–8 and Figure 5–9, respectively) hold the addresses for the next
read transfer and write transfer, respectively.
SOURCE ADDRESS
DESTINATION ADDRESS
As indicated in Table 5–3, the SRC DIR and DST DIR fields can set the index
to increment by element size, decrement by element size, use a global index
value, or not affect the DMA channel source and destination address registers,
respectively. By default, these values are set to 00b to disable address modifi-
cation. If incrementing or decrementing is selected, the amount of the address
adjustment is determined by the size of the element size in bytes. For example,
if the source address is set to increment and 16-bit halfwords are being trans-
ferred, then the address is incremented by 2 after each read transfer.
RW, +x
RW, +x
0
0