Seamless Sdram Write - Texas Instruments TMS320C6201 Reference Manual

Tms320c6000 series peripherals
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SDRAM Interface
Figure 9–29. Seamless SDRAM Write
ACTV B0
ECLKOUT
CEx
BE[3:0]
EA[21:13]
EA[11:2]
EA12
ED[31:0]
SDRAS
SDCAS
SDWE
9-42
Seamless write transfers are accomplished in the same way. First, bank 0 is
opened and after Trcd cycles, the write burst can begin. During the first write
burst, a page in bank 1 can be opened. This allows the write to bank 1 to begin
immediately after the write burst to bank 0 ends, as shown in Figure 9–29.
Trcd = 3
B0
R
R
Write B0,n ACTV B1
BE0
BE1
BE1
B0
B1
Cn
R
R
B0,n
B0,n+1
B0,n+2
Write B1,m
BE2
BE0
BE1
B1
Cm
B0,n+3
B1,m
B1,m+
BE2
B1,m+1

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