8.3.1
Expansion Bus Host Port Registers
The external master on the expansion bus uses the XCNTL signal to select
which internal register is being accessed. The state of this pin selects whether
access is made to the expansion bus internal slave address (XBISA) register
or, expansion bus data (XBD) register. In addition to that, the external master
has access to the entire memory map of the DSP, including memory-mapped
registers.
Table 8–3 summarizes the registers that the expansion bus host port uses for
communication between the host device and the CPU.
Table 8–3. Expansion Bus Host Port Registers
Register
Register
Abbreviation
Name
XBHC
Expansion
Bus Host
Port Control
XBEA
Expansion
Bus External
Address
XBIMA
Expansion
Bus Internal
Master
Address
XBISA
Expansion
Bus Internal
Slave Address
XBD
Expansion
Bus Data
Host Read/
'C6202 Read/
Write Access
Write Access
—
RW
—
RW
—
RW
RW
—
RW
—
Expansion Bus
Expansion Bus Registers
Memory
Mapped
Address
0x0188 000C
0x0188 0024
0x0188 0020
8-7