Emif Sdram Timing Register; Emifsdram Timing Register Field Descriptions - Texas Instruments TMS320C6201 Reference Manual

9.3.4

EMIF SDRAM Timing Register

Figure 9–12. EMIF SDRAM Timing Register
31 26
Reserved
R, +0000 00
† Applies to TMS320C6201/C6202/C6701
‡ Applies to TMS320C6211/C6711 only
Table 9–6. EMIFSDRAM Timing Register Field Descriptions
The SDRAM timing register controls the refresh period in terms of CLKOUT2
cycles for the 'C6201/C6202/C6701 (half of the CPU clock rate), or in terms
of ECLKOUT cycles for the 'C6211/C6711. Optionally, the period field can
send an interrupt to the CPU. Thus, this counter can be used as a general-
purpose timer if SDRAM is not used by the system. The counter field can be
read by the CPU. When the counter reaches 0, it is automatically reloaded with
the period and an interrupt (SDINT) is sent to the interrupt selector. See section
9.4.3 for more information on SDRAM refresh.
Figure 9–12 and Table 9–6 describe the fields of the SDRAM timing register.
The 'C6211/C6711 can control the number of refreshes performed when the
refresh counter expires via the XRFR field. Up to four refreshes can be per-
formed when the refresh counter expires.
25 24 23
XRFR ‡
†
R, +0 R, +0000 1000 0000
‡
RW,+00 R, +0101 1101 1100
Field
PERIOD
COUNTER
XRFR ‡
† Applies to TMS320C6201/C6202/C6701
‡ Applies to TMS320C6211/C6711 only
12
COUNTER
†
‡
Description
† Refresh period in CLKOUT2 cycles
‡ Refresh period in ECLKOUT cycles
Current value of the refresh counter
‡ Extra refreshes: controls the number of refreshes per-
formed to SDRAM when the refresh counter expires.
External Memory Interface
EMIF Registers
11
PERIOD
†
RW, +0000 1000 0000
‡
RW, +0101 1101 1100
0
9-17