Asynchronous Host Port Mode - Texas Instruments TMS320C6201 Reference Manual

8.5.3

Asynchronous Host Port Mode

Table 8–17. Expansion Bus Pin Description (Asynchronous Host Port Mode)
Signal Signal
Symbol Type
XCS I
XD[31:0] I/O/Z
XBE[3:0] I
XCNTL I
XW/R I
XRDY O/Z
This mode is slave only, it uses a 32-bit data path, and it is similar to the HPI
on the 'C6201. The asynchronous host port mode is used to interface to asyn-
chronous microprocessor buses.
A list of the signals when the expansion bus operates in the asynchronous host
port mode is given in Table 8–17.
Signal
Count Signal Name
1 Chip Select
32 Data Bus
4 Byte Enables
1 Control Signal
1 Read/Write
1 Ready Out
The XCNTL signal selects which internal register the host is accessing. The
state of this pin selects if access is made to the expansion bus internal slave
address (XBISA) register or, expansion bus data (XBD) register.
Expansion Bus Host Port Operation
Signal Function
Selects the 'C6202 as a target of an external master.
Functionality of these signals is the same as on the
'C6201 HPI (during a read XBE do not matter). During
a write:
BE3 byte enable 3– XD[31:24]
BE2 byte enable 2– XD[23:16]
BE1 byte enable 1– XD[15:8]
BE0 byte enable 0– XD[7:0]
This signal selects between XBD and XBISA register.
XCNTL=0, access is made to the XBD register
XCNTL=1, access is made to the XBISA register
Polarity of this signal is configured during boot.
Ready signal indicates normally not ready condition.
This signal is always driven in asynch host mode when
the 'C6202 does not own the bus.
Expansion Bus 8-41