Dma Controller Data Bus Block Diagram - Texas Instruments TMS320C6201 Reference Manual

5.11 DMA Controller Structure
Figure 5–14. DMA Controller Data Bus Block Diagram
EMIF read
Data memory read
Program memory read
Peripheral bus read
Auxiliary write
DMA read buses
5.11.1 Read and Write Buses
Figure 5–14 shows the internal data movement paths of the DMA controller,
including data buses and internal holding registers.
CH0 holding
CH1 holding
CH2 holding
CH3 holding
AUX
Each DMA channel can independently select one of four sources and destinations:
EMIF
Internal program memory
Internal data memory
Internal peripheral bus
Read and write buses from each source interface to the DMA controller.
The auxiliary channel also has read and write buses. However, since the auxiliary
channel provides address generation for the DMA, the naming convention of its
buses differs. For example, data writes from the auxiliary channel through the
DMA controller are performed through the auxiliary write bus. Similarly, data
reads from the auxiliary channel through the DMA controller are performed
through the auxiliary read bus.
Burst FIFO
Direct Memory Access (DMA) Controller
DMA Controller Structure
EMIF write
Data memory write
Program memory write
Peripheral bus write
Auxiliary read
5-35