Programmable Asram Parameters - Texas Instruments TMS320C6201 Reference Manual

9.6.1.2 16-Bit ROM Mode
9.6.2

Programmable ASRAM Parameters

In 16-bit ROM mode, the address is left-shifted by 1 to create a half-word address
on EA to access 16-bit-wide ROM. The EMIF always packs two consecutive half-
words aligned on a 4-byte boundary (byte address = 4N) into a word access. The
halfwords are fetched in the following address order: 4N, 4N + 2. Halfwords are
packed into the 32-bit word from the most significant halfword to the least signifi-
cant halfword in the following little-endian order: 4N + 2, 4N.
The EMIF allows a high degree of programmability for shaping asynchronous
accesses. The programmable parameters that allow this are:
Setup: The time between the beginning of a memory cycle (CE low, ad-
dress valid) and the activation of the read or write strobe
Strobe: The time between the activation and deactivation of the read
(ARE) or write strobe (AWE)
Hold: The time between the deactivation of the read or write strobe and the
end of the cycle (which can be either an address change or the deactivation
of the CE signal)
For the 'C6201/C6202/C6701 these parameters are programmable in terms
of CPU clock cycles via fields in the EMIF CE space control registers. For the
'C6211/C6711, these parameters are programmed in terms of ECLKOUT
cycles. Separate set-up, strobe, and hold timing parameters are available for
read and write accesses. Minimum values for ASRAM are as follows:
SETUP 1 (0 treated as 1)
STROBE 1 (0 treated as 1)
HOLD 0
On the 'C6201/C6202/C6701 first access in a set of consecutive accesses
or a single access, the setup period has a minimum count of 2.
Asynchronous Interface
External Memory Interface 9-53