Reset State Of Mcbsp Pins - Texas Instruments TMS320C6201 Reference Manual

Table 11–8. Reset State of McBSP Pins
McBSP
Direction
Pins
DR I
CLKR I/O/Z
FSR I/O/Z
CLKS I
DX O/Z
CLKX I/O/Z
FSX I/O/Z
CLKS I
Device Reset
McBSP Reset
(RESET = 0)
Receiver Reset (RRST = 0 and GRST = 1)
Input Input
Input Known state if input; CLKR if output
Input Known state if input; FSRP(inactive state) if output
Input Input
Transmitter Reset (XRST = 0 and GRST = 1)
High impedance High impedance
Input Known state if input; CLKX if output
Input Known state if input; FSXP(inactive state) if output
Input Input
Device reset or McBSP reset: When the McBSP is reset by device reset
or McBSP reset, the state machine is reset to its initial state. All counters
and status bits are reset. This includes the receive status bits RFULL,
RRDY, and RSYNCERR and the transmit status bits XEMPTY, XRDY, and
XSYNCERR.
Device reset: When the McBSP is reset due to device reset, the entire se-
rial port (including the transmitter, receiver, and the sample rate generator)
is reset. All input-only pins and 3-state pins should be in a known state. The
output-only pin, DX, is in the high impedance state. Since the sample rate
generator is also reset (GRST = 0), the sample rate generator clock,
CLKG, is driven by a divide-by-2 internal clock source, and the frame sync
signal, FSG, is not generated. The internal clock source for the
'C6211/C6711 is CPU clock, while the internal clock source for
'C6211/C6711 is CPU/2 clock (half of the CPU clock frequency). See
section 11.5.1.2 for more information on sample rate generator reset.
When the device is pulled out of reset, the serial port remains in the reset
condition ((R/X)RST = FRST = 0). In this reset condition, the serial port
pins can be used as general-purpose I/O (see section 11.8).
Data Transmission and Reception
Multichannel Buffered Serial Ports 11-19