Texas Instruments TMS320C6201 Reference Manual page 330

McBSP Interface Signals and Registers
Table 11–6. Pin Control Register (PCR) Field Descriptions (Continued)
Name Function
CLKRM Receiver clock mode
Case 1: Digital loopback mode not set (DLB = 0) in SPCR
CLKRM = 0: Receive clock (CLKR) is an input driven by an external clock.
CLKRM = 1: CLKR is an output pin and is driven by the sample rate generator.
Case 2: Digital loopback mode set (DLB = 1) in SPCR
CLKRM = 0: Receive clock (not the CLKR pin) is driven by the transmit clock
CLKRM = 1: CLKR is an output pin and is driven by the transmit clock. The transmit
CLKXM Transmitter clock mode
CLKXM = 0: Transmitter clock is driven by an external clock with CLKX as an input
CLKXM = 1: CLKX is an output pin and is driven by the internal sample rate genera-
During SPI mode (CLKSTP in SPCR is a nonzero value):
CLKXM = 0: McBSP is a slave and (CLKX) is driven by the SPI master in the system.
CLKXM = 1: McBSP is a master and generates the transmitter clock (CLKX) to drive
CLKS_STAT CLKS pin status. Reflects the value on the CLKS pin when selected as a general-pur-
pose input.
DX_STAT DX pin status. Reflects the value driven onto the DX pin when selected as a general-
purpose output.
DR_STAT DR pin status. Reflects the value on the DR pin when selected as a general-purpose
input.
FSRP Receive frame synchronization polarity
FSRP = 0: Frame synchronization pulse FSR is active high
FSRP = 1: Frame synchronization pulse FSR is active low
FSXP Transmit frame synchronization polarity
FSXP = 0: Frame synchronization pulse FSX is active high
FSXP = 1: Frame synchronization pulse FSX is active low
11-12
(CLKX), which is based on the CLKXM bit in PCR. CLKR is in high im-
pedance.
clock is derived from CLKXM bit in the PCR.
pin.
tor.
CLKR is internally driven by CLKX.
its receiver clock (CLKR) and the shift clock of the SPI-compliant slaves
in the system.
Section
11.5.2.6
and
11.8
11.5.2.7
and
11.8
11.7
11.8
11.8
11.8
11.3.4.1
and
11.8
11.3.4.1
and
11.8