Tms320C6211/C6711 Block Diagram - Texas Instruments TMS320C6201 Reference Manual

Figure 7–2. TMS320C6211/C6711 Block Diagram
External
memory
interface
(EMIF)
Multichannel
buffered
serial port 1
(McBSP 1)
Multichannel
buffered
serial port 0
(McBSP 0)
Host port
interface
(HPI)
Power down logic
'C6211/C6711 Digital Signal Processor
As with the 'C6201/'C6701 HPI, the 'C6211/C6711 HPI allows an external host
processor to perform read and write accesses from/to the 'C6211/C6711 ad-
dress space. Unlike the 'C6201 HPI interface which uses the DMA auxiliary
channel to perform accesses, the 'C6211/C6711 the HPI ties directly into inter-
nal address generation hardware. No specific EDMA channel is used for per-
forming 'C6211/C6711 HPI accesses. Instead, the internal address generation
hardware handles the read/write requests and accesses.
Enhanced
DMA
controller
Timer 1
L1P
controller
Instruction fetch
Instruction dispatch
Instruction decode
Data path 1
A register file
L1 S1 M1 D1
controller
Timer 0
L1P cache direct mapped
4K bytes
CPU core
Control registers
In-circuit emulation
Data path 2
B register file
D2 M2 S2
L1D cache
L1D
2-way set
associative
4K bytes
Host-Port Interface
Overview
L2
7-3