Hpi External Interface Signals - Texas Instruments TMS320C6201 Reference Manual

7.2 HPI Signal Descriptions
Table 7–1. HPI External Interface Signals
Signal
Signal Type
Name
HD[15:0] I/O/Z
HCNTL[1:0] I
HHWIL I
HAS I
HBE[1:0] I
HR/W I
HCS I
HDS[1:2] I
HRDY O
HINT O
{
I = input, O = output, Z = high impedance
7.2.1 Data Bus: HD[15:0]
7.2.2 Access Control Select: HCNTL[1:0]
The external HPI interface signals implement a flexible interface to a variety
of host devices. Table 7–1 lists the HPI pins and their functions. The remainder
of this section discusses the pins in detail.
Signal
{
Host Connection
Count
16 Data bus
2 Address or control lines
1 Address or control lines
1 Address latch enable (ALE),
address strobe, or unused
(tied high)
2 Byte enables
1 Read/write strobe, address
line, or multiplexed address/
data
1 Address or control lines
1 Read strobe and write
strobe or data strobe
1
1 Asynchronous ready
1 Host interrupt input
HD[15:0] is a parallel, bidirectional, 3-state data bus. HD is placed in the high-
impedance state when it is not performing an HPI read access.
HCNTL[1:0] indicate which internal HPI register is being accessed. The states
of these two pins select access to the HPI address (HPIA), HPI data (HPID), or
HPI control (HPIC) registers. Additionally, the HPID register can be accessed
with an optional automatic address increment. Table 7–2 describes the
HCNTL[1:0] bit functions.
HPI Signal Descriptions
Signal Function
HPI access type control
Halfword identification input
Differentiation between address
2nd data values on multiplexed ad-
dress/data host
Data write byte enables
Read/write select
Data strobe inputs
Data strobe inputs
Ready status of current HPI access
Interrupt signal to host
Host-Port Interface 7-7