Tms320C6202 Data Memory Controller Block Diagram - Texas Instruments TMS320C6201 Reference Manual

3.5 TMS320C6202 Data Memory Controller
Figure 3–2. TMS320C6202 Data Memory Controller Block Diagram
Block 0
(64K bytes)
Bank 3
Bank 2
Bank 1
Bank 0
Table 3–5. Internal Data RAM Address Mapping
The TMS320C6202 data memory controller (DMEMC) provides all of the func-
tionality available in the TMS320C6201 revision 3. The C6202 DMEMC con-
tains 128K bytes of RAM organized in two blocks of four banks each. Each
bank is 16 bits wide. The DMEMC for the C6202 operates identically to the
C6201 DMEMC, the DMA controller or side A or side B of the CPU can simulta-
neously access two different banks without conflict. Figure 3–2 shows a block
diagram of the connections between the C6202 CPU, DMEMC, and memory
blocks. Table 3–5 shows the memory range occupied by each block of internal
data RAM.
Data path B
32
16
16
Data memory controller
16
16
32
Peripheral
bus
controller
Block 0 8000 0000h – 8000 FFFFh
Block 1 8001 0000h – 8001 FFFFh
TMS320C6202 Data Memory Controller
C62x CPU
Data path A
32 32
(DMEMC)
32 32
External DMA bus
memory controller
interface
TMS320C6202 Program and Data Memory
32
Block 1
(64K bytes)
16
16
16
16
Bank 3
Bank 2
Bank 1
Bank 0
3-7