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Expansion Bus Arbitration
8.6 Expansion Bus Arbitration
Table 8–18. XARB Bit Value and XHOLD/XHOLDA Signal Functionality
8.6.1
Internal Bus Arbiter Enabled
8-44
Two signals, XHOLD and XHOLDA, are provided for bus arbitration. The
internal bus arbiter is disabled or enabled depending on the value on the
expansion data bus during reset.
The XARB bit in the expansion bus global control register indicates if the inter-
nal bus arbiter is enabled or disabled. This is shown in Table 8–18.
XARB Bit (Read Only)
0 (Indicates disabled internal bus arbiter)
1 (Indicates enabled internal bus arbiter)
If the internal bus arbiter is enabled, the 'C6202 wakes up from reset as the
bus master. If internal bus arbiter is disabled, the 'C6202 wakes up from reset
as the bus slave. The DMA controller releases the expansion bus between
frames if a DMA block transfer is in progress. When the 'C6202 releases the
expansion bus, the host port signals become tristated, except for the I/O port
signals (XWE/XWAIT, XOE, XRE, XCE[3:0], and XFCLK) which are not af-
fected.
In this mode the 'C6202 owns the expansion bus by default. The 'C6202 wakes
up from reset as the master of the expansion bus, and all other devices must
request the bus from 'C6202. This mode is preferred when connecting one
'C6202 to a PCI interface chip.
When the TMS320C6202 owns the expansion bus, both XHOLD (input) and
XHOLDA (output) are low. XHOLD is asserted by an external device to request
use of the expansion bus. The 'C6202 asserts XHOLDA when bus request is
granted. The expansion bus is not granted unless requested by XHOLD.
Figure 8–25 illustrates XHOLD and XHOLDA functionality when the internal
bus arbiter is enabled. In this mode the DSP grants the expansion bus to the
requester only if no internal transfer requests to the expansion bus are
pending.
XHOLD
XHOLDA
Output
Input
Input
Output
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