Sdram Initialization; Monitoring Page Boundaries - Texas Instruments TMS320C6201 Reference Manual

9.4.1

SDRAM Initialization

9.4.2

Monitoring Page Boundaries

The EMIF performs the necessary tasks to initialize SDRAM if any of the CE
spaces are configured for SDRAM. An SDRAM initialization is requested by
a write of 1 to the INIT bit in the EMIF SDRAM control register.
The steps of an initialization are as follows:
1) Send a DCAB command to all CE spaces configured as SDRAM.
2) Send three refresh commands.
3) Send an MRS command to all CE spaces configured as SDRAM.
The DCAB cycle is performed immediately after reset, provided the HOLD input
is not active (a host request). If HOLD is active, the DCAB command is not per-
formed until the hold condition is removed. In this case the external requester
should not attempt to access any SDRAM banks, unless it performs SDRAM
initialization and control itself.
Because SDRAM is a paged memory type, the EMIF SDRAM controller monitors
the active row of SDRAM so that row boundaries are not crossed during the
course of an access. To accomplish this monitoring, the EMIF stores the address
of the open page and performs compares against that address for subsequent
accesses to the SDRAM bank. For the 'C6201/C6202/C6701, this storage and
comparison is performed independently for each CE space, so that a single page
can be open in each CE space.
The number of address bits compared is a function of the page size programmed
in the SDWID field in the EMIF SDRAM control register for the
'C6201/C6202/C6701. If SDWID = 0, the EMIF expects CE spaces configured
as SDRAM to have four 8-bit-wide SDRAMs that have page sizes of 512. Thus,
the logical byte address bits compared are 23–11. If SDWID = 1, the EMIF ex-
pects CE spaces with SDRAM to have two 16-bit-wide SDRAMs that have page
sizes of 256. Thus, the logical byte address bits compared are 23–10. The logical
address bits 25 to 24 determine their CE space. If a page boundary is crossed
during an access to the same CE space, the EMIF performs a DCAB com-
mand and starts a new row access.
SDRAM Interface
External Memory Interface 9-25