SDRAM Interface
Figure 9–19. TMS320C6211/C6711 Mode Register Value (0032h)
13
EA15
EA14
6
5
EA8
EA7
Read latency
0
1
Figure 9–20. TMS320C6211/C6711 Mode Register Value (0022h)
13
EA15
EA14
6
5
EA8
EA7
Read latency
0
1
Table 9–12. TMS320C6211/C6711 Implied SDRAM Configuration by MRS
9-30
The 'C6211/C6711 uses a mode register value of either 0032h or 0022h. The
register value and description are shown in Figure 9–19 and Figure 9–20.
Both values program a default burst length of four words for both reads and
writes. The value actually used depends on the CASL parameter defined in the
SDRAM extension register. If the CAS latency is three, 0032h is written. If the
CAS latency is two, 0022h is written during the MRS cycle. Table 9–12 sum-
marizes.
12
11
EA13
Rsvd
0000
4
EA6
1
12
11
EA13
Rsvd
0000
4
EA6
0
10
9
SDA10
EA11
Write burst
length
0
3
2
EA5
EA4
S/I
0
10
9
SDA10
EA11
Write burst
length
0
3
2
EA5
EA4
S/I
0
Field
Write burst length
Read latency
Serial/interleave burst type
Burst length
8
7
EA10
EA9
Rsvd
00
1
0
EA3
EA2
Burst length
010
8
7
EA10
EA9
Rsvd
00
1
0
EA3
EA2
Burst length
010
CASL = 0
CASL = 1
4 words
4 words
2 cycles
3 cycles
Serial
Serial
4 words
4 words