Texas Instruments TMS320TCI6482 Design Manual
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Texas Instruments TMS320TCI6482 Design Manual

Texas Instruments TMS320TCI6482 Design Manual

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TMS320TCI6482 Design Guide and Migration from
Rick Hennessy and Douglas Harrington
This document describes system design considerations for the TMS320TCI6482
(TCI6482). It also gives comparisons to designing with the TMS320TCI100 (TCI100) for
those familiar with that device. The objective of this document is to cover system
design considerations for the TCI6482. Those familiar with the TCI100 can use the
comparisons to migrate a TCI100 design to the TCI6482. In some cases there is
information overlapping with the TCI6482 data manual. If the information does not
match the data manual information takes precedence.
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ABSTRACT
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List of Figures
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List of Tables
TMS320TCI6482 Design Guide and Migration from TMS320TCI100
Digital Signal Processing Solutions
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Summary of Contents for Texas Instruments TMS320TCI6482

  • Page 1: Table Of Contents

    Digital Signal Processing Solutions ABSTRACT This document describes system design considerations for the TMS320TCI6482 (TCI6482). It also gives comparisons to designing with the TMS320TCI100 (TCI100) for those familiar with that device. The objective of this document is to cover system design considerations for the TCI6482.
  • Page 2 TCP2 Register Changes on TCI6482 ..........GPIO/Interrupt Comparison: TCI6482 vs TCI100 ............Timer Comparison: TCI6482 vs TCI100 ..............SRIO PLL Multiplier Settings ........... JTAG/Emulation Comparison: TCI6482 vs TCI100 TMS320TCI6482 Design Guide and Migration from TMS320TCI100 SPRAAC7B – April 2006 Submit Documentation Feedback...

  • Page 3: Tci6482 Documentation

    • Application Notes – EDMA v3.0 (EDMA3) Migration Guide for TMS320TCI648x DSP (SPRAAC1) – Implementing Serial Rapid I/O PCB Layout on a TMS320TCI6482 Hardware Design (SPRAAB0) – Implementing DDR2 PCB Layout on the TMS320TCI6482 (SPRAAA9) – Using IBIS Models for Timing Analysis (SPRA839) •...

  • Page 4: Tci6482 Features, Comparison To Tci100 Processor

    (Configurable as (Cache only) cache and SRAM) 2048K-Byte 1024K-Byte CPU MegaModule Revision ID Register Read value: 0x0 Revision ID (MM_REVID[15:0]) (silicon revision 1.1) Byte address = 0x01812000 TMS320TCI6482 Design Guide and Migration from TMS320TCI100 SPRAAC7B – April 2006 Submit Documentation Feedback...

  • Page 5: Device Identification (Id)

    Modification will be needed to account for the different physical dimensions of package and pin out. Changes in substrate may also affect the thermal characteristics of the package used for TCI6482. See the TMS320TCI6482 Communications Infrastructure Digital Signal Processor (SPRS246) for additional information regarding package characteristics.

  • Page 6: Device Configurations And Initialization

    For details on setting the CLKIN1 PLL multiplier and divider settings refer to section 6.1 and the TMS320TCI648x DSP PLL Controller Reference Guide (SPRU806). TMS320TCI6482 Design Guide and Migration from TMS320TCI100 SPRAAC7B – April 2006...
  • Page 7 ROM). In addition, a first level boot loader (loaded using one of those interfaces) can configure the Ethernet or Utopia interfaces for a secondary boot load. For a summary of the boot modes supported refer to the TCI6482 data manual. For details regarding boot modes, refer to the TMS320TCI6482 Bootloader User's Guide document.

  • Page 8: Clocking

    6.1.1 Clock PLL and PLL Controller A description of the PLLs and PLL controllers along with register definitions can be found in the TMS320TCI6482 Communications Infrastructure Digital Signal Processor (SPRS246). Table 4 shows the clocking differences between the TCI6482 and the TCI100.

  • Page 9: Reference Clock Requirements

    DDR2 subsystem, must be low jitter. The SRIO reference clock (RIOCLK, RIOCLK) requires a differential low jitter clock source and proper termination. It is also assumed that multiple TMS320TCI6482 devices may be used on a board so the proposed system solutions include clock fanout buffers.

  • Page 10: Clkin1, Clkin2 Single Device Clock Solution

    6.3.2.2 Fanout Solutions For systems with multiple TMS320TCI6482 devices it may be preferred to use one oscillator and a fanout buffer instead of multiple oscillators. This would allow for fewer components as well as lower cost. The fanout buffer increases the jitter at the clock input so care must be taken in selecting the combination of oscillator and fanout buffer.

  • Page 11: Pll1, Pll2 Multiple Device Clock Solution

    AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (scaa059). For information on DC coupling refer to DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML (scaa062) . SPRAAC7B – April 2006 TMS320TCI6482 Design Guide and Migration from TMS320TCI100 Submit Documentation Feedback...

  • Page 12: Rioclk Single Device Lvds Clock Solution

    6.3.3.1 Single Device Solution It is assumed that the source clock is an oscillator on the same board as the TMS320TCI6482. Use of distributed clocks may require a jitter cleaner device such as the CDCM7005 (refer to http://focus.ti.com/docs/prod/folders/print/cdcm7005.html) or the CDCL6010. If an on-board oscillator is used with one TMS320TCI6482 no other components should be needed except for terminations.

  • Page 13: Rioclk Multiple Devices Lvds Clock Solution

    RIOCLK Example: RIOCLK# Pletronics PE77D 0.01uF CLKN 50 ohm 50 ohm CLK9# RIOCLK 0.01uF DSP10 RIOCLK# 50 ohm Figure 6. RIOCLK Multiple Devices LVPECL Clock Solution SPRAAC7B – April 2006 TMS320TCI6482 Design Guide and Migration from TMS320TCI100 Submit Documentation Feedback...

  • Page 14: Power Supply

    VSS. Removing power from these interfaces will result in the inability to boundary scan test these interfaces. Refer to the data manual for details. TMS320TCI6482 Design Guide and Migration from TMS320TCI100 SPRAAC7B – April 2006 Submit Documentation Feedback...

  • Page 15: Power Supply Generation

    8. The filter component shown is a from Murata part. If a different part is cross-referenced, the frequency envelope must be considered. This solution has been tested. SPRAAC7B – April 2006 TMS320TCI6482 Design Guide and Migration from TMS320TCI100 Submit Documentation Feedback...

  • Page 16: Recommended Power Supply Filter

    I/Os. This is done through a simple voltage divider as shown in Figure 9. More details on VREFSSTL can be found in: Implementing DDR2 PCB Layout on the TMS320TCI6482 (SPRAAA9). Note that if the RGMII interface is not used and is disabled, VREFHSTL can be connected to directly to VSS. DVDD18 1K 1% 0.1uF...
  • Page 17 Power requirements are highly dependent on the usage of the device. This includes which peripherals are used as well as the operating frequencies. In order to generate an estimate of the TCI6482 power for a particular application, refer to the TMS320TCI6482 Preliminary Power Consumption Summary. Power Supply Layout Recommendations Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize inductance and resistance in the power delivery path.

  • Page 18: Multiple Dsp Remote Sense Connections

    GND plane near the DSP using a 0 ohm resistor. The single DSP remote sense connections are shown in Figure TMS320TCI6482 Design Guide and Migration from TMS320TCI100 SPRAAC7B – April 2006 Submit Documentation Feedback...

  • Page 19: Single Dsp Remote Sense Connections

    Larger caps can be placed further away for bulk decoupling. Large bulk caps should be furthest away (but still as close as possible). SPRAAC7B – April 2006 TMS320TCI6482 Design Guide and Migration from TMS320TCI100 Submit Documentation Feedback...

  • Page 20: Bulk Capacitor Examples

    3 * 680uF 2 * 22uF DVDD33 16 * 560pF 330uF 3.3V I/O DVDD 1 * 330uF 333.2 uF 24 * 100nF 32 * 100nF 1 * 330uF TMS320TCI6482 Design Guide and Migration from TMS320TCI100 SPRAAC7B – April 2006 Submit Documentation Feedback...

  • Page 21: O Buffers

    1.25Gbps links. Generally, running fewer high speed links is more power efficient than multiple slower links. • RGMII operation at 1.5V will have lower power consumption than at 1.8V. I/O Buffers SPRAAC7B – April 2006 TMS320TCI6482 Design Guide and Migration from TMS320TCI100 Submit Documentation Feedback...

  • Page 22: Peripheral Section

    Generally, if internal pull-ups or pull-downs are included the pins can be left floating. Any pin that is output only can always be floated. If internal pull-ups and TMS320TCI6482 Design Guide and Migration from TMS320TCI100 SPRAAC7B – April 2006...
  • Page 23 Generally, a synchronous interface is best from a performance standpoint and an asynchronous interface has less performance but is easier to implement. SPRAAC7B – April 2006 TMS320TCI6482 Design Guide and Migration from TMS320TCI100 Submit Documentation Feedback...

  • Page 24: Emifa Comparsion: Tci6482 Vs Tci100

    TMS320TCI6482 Design Guide and Migration from TMS320TCI100 SPRAAC7B – April 2006 Submit Documentation Feedback...

  • Page 25: Hpi Comparison: Tci6482 Vs Tci100

    PTRDY, PIRDY, PDEVSEL, PSTOP, PSERR, PPERR, and PINTA. Typical resistance values are 8.2Kohms but this is dependent on the number of loads. Refer to the PCI specification for details on determining the optimal pull-up value. SPRAAC7B – April 2006 TMS320TCI6482 Design Guide and Migration from TMS320TCI100 Submit Documentation Feedback...

  • Page 26: Pci Comparison: Tci6482 Vs Tci100

    Also, the specific routing topology becomes much more significant as additional DSPs are included. The way to determine the best topology and maximum operating frequency are by performing IBIS simulations. TMS320TCI6482 Design Guide and Migration from TMS320TCI100 SPRAAC7B – April 2006 Submit Documentation Feedback...

  • Page 27: Mcbsp 8 Load Routing Topology

    • TMS320TCI648x DSP Viterbi-Decoder Coprocessor (VCP) Reference Guide (SPRUE09) 9.5.1 Configuration of VCP2 VCP2 needs to be enabled via software after a reset. The VCP2 operates at CPU core clock / 3. SPRAAC7B – April 2006 TMS320TCI6482 Design Guide and Migration from TMS320TCI100 Submit Documentation Feedback...

  • Page 28: Vcp2 Summary Of Changes On Tci6482

    TCI6482 VCP2 Impact Added in ¼ buffer events ½ buffer events ¼ buffer events and ½ buffer Flexibility events Memory Map Yes - Modified Coding Migration TMS320TCI6482 Design Guide and Migration from TMS320TCI100 SPRAAC7B – April 2006 Submit Documentation Feedback...

  • Page 29: Vcp2 Register Changes On Tci6482

    Emulation Support Extrinsic Scaling YES, used in max-log-map Better BER HIU/EDMA Interface Shared HIU 64-bits Dedicated 64-bit bridge Reduced EDMA transfer time Memory Sleep Mode Power efficient SPRAAC7B – April 2006 TMS320TCI6482 Design Guide and Migration from TMS320TCI100 Submit Documentation Feedback...

  • Page 30: Tcp2 Usage Change On Tci6482

    GP2 and GP12-GP15, if selected as GPIOs, can be left floating with a power consumption penalty versus having external pull-up or pull-down resistors. TMS320TCI6482 Design Guide and Migration from TMS320TCI100 SPRAAC7B – April 2006 Submit Documentation Feedback...

  • Page 31: Gpio/Interrupt Comparison: Tci6482 Vs Tci100

    External timer input signals are synchronized to the internal timer clock. Since the timer operates at CPU core / 6, the timer input can be delayed from the timer input as much as one CPU core / 6 period. SPRAAC7B – April 2006 TMS320TCI6482 Design Guide and Migration from TMS320TCI100 Submit Documentation Feedback...

  • Page 32: Timer Comparison: Tci6482 Vs Tci100

    If the I²C signals are not used, the SDA and SCL pins can be left floating. This does cause a slight increase in power due to leakage which can be avoided by having pull-up resistors. TMS320TCI6482 Design Guide and Migration from TMS320TCI100 SPRAAC7B – April 2006...
  • Page 33 CLKIN2 25MHz clock and this RMII reference clock. Therefore it cannot be assumed that aligning CLKIN2 to multiple TCI6482 devices results in aligned RMII interfaces. SPRAAC7B – April 2006 TMS320TCI6482 Design Guide and Migration from TMS320TCI100 Submit Documentation Feedback...
  • Page 34 For more information and additional voltage translation options refer to the following application note: Selecting the Right Level Translation Solution (SCEA035) TMS320TCI6482 Design Guide and Migration from TMS320TCI100 SPRAAC7B – April 2006 Submit Documentation Feedback...

  • Page 35: Hstl To Lvcmos Translation

    This power can be minimized by adding external pull-ups. If the Utopia interface is enabled but some inputs are not used, external pull-ups or pull-downs are needed to put these inputs into valid states. SPRAAC7B – April 2006 TMS320TCI6482 Design Guide and Migration from TMS320TCI100 Submit Documentation Feedback...
  • Page 36 VLYNQ clock rate is 25 MHz (high for 8 ns and low for 32 ns). However, the 8 ns high pulse width requires the circuit board to be designed for 62.5 MHz. TMS320TCI6482 Design Guide and Migration from TMS320TCI100 SPRAAC7B – April 2006...

  • Page 37: Vlynq Clock Divider Example

    9.14 Serial Rapid I/O (SRIO) Relevant documentation for SRIO: • TMS320TCI648x DSP Serial Rapid I/O User's Guide (SPRUE13) • Implementing Serial Rapid IO PCB Layout on a TMS320TCI6482 Hardware Design (SPRAAB0) • TCI6482 System Boot • TCI6482 SRIO/DDR Example Schematics 9.14.1...
  • Page 38 9.14.2 System Implementation of SRIO Refer to the Implementing Serial Rapid IO PCB Layout on a TMS320TCI6482 Hardware Design (SPRAAB0 for information regarding supported topologies and layout guidelines. Suggestions on SRIO reference clocking solutions can be found in Section 6.3.3.

  • Page 39: Jtag/Emulation Comparison: Tci6482 Vs Tci100

    Advanced Emulation pins Trace support 9.17 Rake Search Accelerator (RSA) Both RSAs can be enabled by software after a reset. The RSAs operate at CPU core clock speed. SPRAAC7B – April 2006 TMS320TCI6482 Design Guide and Migration from TMS320TCI100 Submit Documentation Feedback...

  • Page 40: Appendix Atci6482 Rgmii 1.5V/1.8V To 2.5V/3.3V Translation

    As an alternative to the LVCMOS type buffers, a good solution can be found using TVC-type buffers or CBT buffers in a TVC configuration. Texas Instruments has an excellent application note describing the configuration (SCEA035A). An example of this application is shown in Figure A-1 using a CBT3245 in a TVC voltage-clamp configuration.
  • Page 41 Note in all cases the extremely low propagation delay and good edge rates that result with this solution. SPRAAC7B – April 2006 TMS320TCI6482 Design Guide and Migration from TMS320TCI100 Submit Documentation Feedback...

  • Page 42: Vout Vs Vin

    B2 was swept from 0 to 2.5v in 0.1v steps and the waveform at A2 was observed. A 1Meg resistor to GND was connected at A2. TMS320TCI6482 Design Guide and Migration from TMS320TCI100 SPRAAC7B – April 2006 Submit Documentation Feedback...

  • Page 43: 125Mhz Signal From A2 To B2 And From B3 To A3

    Appendix A Figure A-3. 125MHz Signal from A2 to B2 and From B3 to A3 SPRAAC7B – April 2006 TMS320TCI6482 Design Guide and Migration from TMS320TCI100 Submit Documentation Feedback...
  • Page 44 TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions:...

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