Dma Channel Secondary Control Register; Dma Channel Secondary Control Register Field Descriptions - Texas Instruments TMS320C6201 Reference Manual

DMA Registers
Figure 5–3. DMA Channel Secondary Control Register
31
15 14 13
WSYNC WSYNC RSYNC
CLR STAT CLR
RW, RW, RW,
+0 +0 +0
Table 5–4. DMA Channel Secondary Control Register Field Descriptions
Field
SX COND
FRAME COND
LAST COND
BLOCK COND
RDROP COND
WDROP COND
SX IE
FRAME IE
LAST IE
BLOCK IE
RDROP IE
WDROP IE
RSYNC STAT
WSYNC STAT
DMAC EN
RSYNC CLR
WSYNC CLR
5-10
Reserved
R, +0000 0000 0000 0
12 11 10
RSYNC WDROP WDROP RDROP
STAT IE COND
RW, RW, RW,
+0 +0 +0
Description
DMA condition. Each bit indicates a separate condition.
A0 value indicates that the condition is not detected.
A1 value indicates that the condition is detected.
DMA condition interrupt enable
IE = 0: associated condition does not enable DMA channel interrupt
IE = 1: associated condition enables DMA channel interrupt
Read or write synchronization status
STAT = 0: synchronization is not received
STAT = 1: synchronization is received
DMAC pin control
DMAC EN = 000b: DMAC pin is held low.
DMAC EN = 001b: DMAC pin is held high.
DMAC EN = 010b: DMAC reflects RSYNC STAT.
DMAC EN = 011b: DMAC reflects WSYNC STAT.
DMAC EN = 100b: DMAC reflects FRAME COND.
DMAC EN = 101b: DMAC reflects BLOCK COND.
DMAC EN = other: reserved
Read or write synchronization status clear
Read as 0 write 1 to clear associated status
9 8 7 6
RDROP BLOCK BLOCK
IE COND IE COND
RW, RW, RW, RW,
+0 +0 +1 +0
19 18
5 4 3 2
LAST LAST FRAME FRAME
IE COND IE COND
RW, RW, RW, RW,
+0 +0 +0 +0
16
DMAC EN
RW, +000
1 0
SX SX
IE COND
RW, RW,
+0 +0
Section
5.10
5.10.1
5.6.1
5.12
5.6.1