Texas Instruments TMS320C6201 Reference Manual page 39

2.2 Internal Program Memory
2.2.1 Internal Program Memory Modes
The internal program memory contains 64K bytes of RAM or, equivalently, 2K
256-bit fetch packets or 16K 32-bit instructions. The CPU, through the pro-
gram memory controller, has a single-cycle throughput, 256-bit-wide connec-
tion to internal program memory.
The internal program memory can be used in any of four modes which are se-
lected by the program cache control (PCC) field (bits 7–5) in the CPU control
and status register (CSR) as shown in Table 2–1. The modes are:
Mapped: Depending on the memory map selected, the program memory
is located at one of these addresses:
J
0000 0000h–0000 FFFFh for map 1
J
0140 0000h–0140 FFFFh for map 0
In mapped mode, program fetches from the internal program memory ad-
dress return the fetch packet at that address. In the other modes, CPU
accesses to this address range return undefined data. Mapped mode is
the default state of the internal program memory at reset. The CPU cannot
access internal program memory through the data memory controller.
(See Chapter 7, Boot Configuration, Reset, and Memory Map , for informa-
tion about how to select the memory map.)
Cache enabled: In cache enabled mode, any initial program fetch at an ad-
dress causes a cache miss. In a cache miss, the fetch packet is loaded from
the external memory interface (EMIF) and stored in the internal cache
memory, one 32-bit instruction at a time. While the fetch packet is being
loaded, the CPU is halted. The number of wait states incurred depends on
the type of external memory used, the state of that memory, and any conten-
tion for the EMIF with other requests, such as the DMA controller or a CPU
data access. Any subsequent read from a cached address causes a cache
hit, and that fetch packet is sent to the CPU from the internal program
memory without any wait states. Changing from program memory mode to
cache enabled mode flushes the program cache. This mode transition is the
only means to flush the cache.
Cache freeze: During a cache freeze, the cache retains its current state.
A program read of a frozen cache is identical to a read of an enabled cache
except that on a cache miss the data read from the external memory inter-
face is not stored in the cache. A subsequent read of the same address
causes a cache miss, and the data is again fetched from external memory.
TMS320C6201/C6701 Program and Data Memory
Internal Program Memory
2-3