Data Memory Organization (Tms320C6201 Revision 3) - Texas Instruments TMS320C6201 Reference Manual

2.6.2 TMS320C6201 Revision 3
Table 2–3. Data Memory Organization (TMS320C6201 Revision 3)
Bank 0
First address 80000000
(Block 0) 80000008
80007FF0
Last address 80007FF8
(Block 0)
First address 80008000
(Block 1) 80008008
8000FFF0
Last address 8000FFF8
(Block 1)
The 64K bytes of internal data RAM are organized as two blocks of 32K bytes
located from address 8000 0000h to 8000 7FFFh and 8000 8000h to
8000 FFFFh. The DMA controller or side A and side B of the CPU can simulta-
neously access any portion of the internal memory without conflict, when using
different blocks. Both blocks are organized as four 4K banks of 16-bit halfwords.
Therefore you do not have to consider the address within a block if simultaneous
accesses occur to different blocks. Accesses to different blocks never cause per-
formance penalties. Both CPU and DMA can still simultaneously access data that
resides in different banks within the same block without a performance penalty.
To avoid performance penalties, you have to pay attention to address LSBs
when the two accesses involve data in the same block. This organization also
allows the two CPU data ports, A and B, to simultaneously access neighboring
16-bit data elements inside the block without a resource conflict.
Bank 1
80000001 80000002
80000009 8000000A
80007FF1 80007FF2
80007FF9 80007FFA
80008001 80008002
80008009 8000800A
8000FFF1 8000FFF2
8000FFF9 8000FFFA
TMS320C6201/C6701 Program and Data Memory
Bank 2
80000003 80000004
8000000B 8000000C
80007FF3 80007FF4
80007FFB 80007FFC
80008003 80008004
8000800B 8000800C
8000FFF3 8000FFF4
8000FFFB 8000FFFC
Internal Data Memory Organization
Bank 3
80000005 80000006
8000000D 8000000E
80007FF5 80007FF6
80007FFD 80007FFE
80008005 80008006
8000800D 8000800E
8000FFF5 8000FFF6
8000FFFD 8000FFFE
80000007
8000000F
80007FF7
80007FFF
80008007
8000800F
8000FFF7
8000FFFF
2-11