Edma Element And Frame/Array Count Updates - Texas Instruments TMS320C6201 Reference Manual

Element and Frame/Array Count Updates
6.11 Element and Frame/Array Count Updates
Table 6–6. EDMA Element and Frame/Array Count Updates
6.11.1 Element Count Reload (ECRLD)
6-28
The EDMA parameter RAM has 16-bit unsigned values of element count (EC)
and frame count (FC) each. Additionally, it also holds 16-bit signed values
each for the element index (EIX) and frame index (FIX). The maximum number
of elements in a frame or an array (for 2D transfers) is 65535. The maximum
number of frames in a block is 65536.
The element count and frame count are updated in the corresponding event's
transfer entry depending on the type of transfer (2D or non-2D) and the syn-
chronization type as shown in Table 6–6.
Synchronization Transfer Mode
Read/write (FS=0) Non-2D;
(2DS&2DD=0)
Read/write (FS=0) 2D;
(2DS|2DD=1)
Frame (FS=1) Non-2D;
(2DS&2DD=0)
Frame (FS=1) 2D;
(2DS|2DD=1)
† No frame/array count update occurs if the frame/array count is zero (FC = 0).
There is a special condition for reloading the element count for read/write syn-
chronized (FS = 0), non-2D transfers. In this case the address is updated by
element size or element/frame index depending on SUM/DUM fields. See the
first row in Table 6–7. Therefore, the EDMA controller keeps track of the ele-
ment count to update the address. When a read/write sync event occurs at the
end of a frame (EC = 1), the EDMA controller sends off the transfer request,
and reloads the EC from the element count reload field in the parameter RAM.
This element count reload occurs when element count is one, and the frame
count is non-zero. For all other types of transfers, the 16-bit element count re-
load field is not used because the address generation hardware tracks the ad-
dress directly.
Element Count Frame/Array
Count Update †
Update
–1 –1
(reload if EC = 1) (if element count = 1)
See section
6.11.1
None –1
None –1
None None